uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 54

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 61 Description of register bits (address 21H)
Table 62 ADC input amp PGA gain settings
Table 63 Register address 22H
Table 64 Description of register bits (address 22H)
2003 Apr 10
14 to 12
Symbol
Default
Symbol
Default
15 to 13
11 to 8 PGA_GAIN_CTRLL[3:0]
7 to 4
3 to 0
Stereo audio codec with SPDIF interface
BIT
BIT
BIT
BIT
15
12
PGA_GAIN_
PGA_GAIN_
CTRLR3
CTRLL3
MT_ADC
PGA_GAIN_CTRLR[3:0]
ADCPOL_INV
0
0
0
0
0
0
0
0
1
SYMBOL
15
0
7
0
SYMBOL
14
0
6
0
PGA_GAIN_
PGA_GAIN_
reserved
ADC polarity control. If this bit is logic 0 then the ADC input is not inverted; if this bit is
logic 1 then the ADC input is inverted.
CTRLR2
CTRLL2
0
0
0
0
1
1
1
1
0
Mute ADC. If this bit is logic 0 then the ADC is not muted; if this bit is logic 1 then
the ADC is muted.
reserved
PGA gain control left channel. Value to program the gain of the left input
amplifier. There are nine settings (see Table 62).
reserved
PGA gain control right channel. Value to program the gain of the right input
amplifier. There are nine settings (see Table 62).
13
0
5
0
ADCPOL_INV
PGA_GAIN_
PGA_GAIN_
CTRLR1
CTRLL1
12
0
4
0
0
0
1
1
0
0
1
1
0
54
DESCRIPTION
11
DESCRIPTION
0
3
0
PGA_GAIN_
PGA_GAIN_
CTRLR0
CTRLL0
0
1
0
1
0
1
0
1
0
10
0
2
0
DC_SKIP
Preliminary specification
9
0
1
1
UDA1355H
GAIN (dB)
HP_EN_DEC
12
15
18
21
24
0
3
6
9
8
0
0
1