uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 39

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12 REGISTER MAPPING
In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the
mapping of the readable and writable registers is given. The explanation of the register definitions are explained in
Sections 12.2 and 12.3.
12.1
Table 24 Register map settings
2003 Apr 10
System settings
00H
01H
02H
03H
04H
Interpolator
10H
11H
12H
13H
14H
18H
19H
1AH
1BH
1CH
1DH
1EH
Decimator
20H
21H
22H
28H
SPDIF input
30H
40H
59H
5AH
5BH
5CH
ADDRESS
Stereo audio codec with SPDIF interface
Address mapping
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
crystal clock power-on setting; crystal clock and PLL divider settings; MODE and WS detector
settings; clock output setting
I
I
reserved for manufacturers evaluation and should be kept untouched for normal operation
analog power and clock settings
master volume control settings
mixer volume settings
sound feature and bass boost and treble settings
gain select; de-emphasis and mute settings
DAC polarity; noise shaper selection; mixer; source selection; silence detector and interpolator
oversampling settings
mute and silence detector status read-out
resonant bass boost coefficient k1 setting
resonant bass boost coefficient km setting
resonant bass boost coefficient a1 setting
resonant bass boost coefficient a2 setting
resonant bass boost coefficient b1 setting
resonant bass boost coefficient b2m setting
ADC gain settings
ADC mute and PGA gain settings;
ADC polarity and DC cancellation settings
mute status and overflow ADC read-out
SPDIF power control and SPDIF input settings
reserved for manufacturers evaluation and should be kept untouched for normal operation
SPDIF LOCK; bit error information and SPDIF encoder output status read-out
SPDIF input status bits 15 to 0 left channel read-out
SPDIF input status bits 31 to 16 left channel read-out
SPDIF input status bits 39 to 32 left channel read-out
2
2
S-bus output format settings
S-bus input format settings
39
DESCRIPTION
Preliminary specification
UDA1355H