n80930hf Intel Corporation, n80930hf Datasheet
n80930hf
Manufacturer Part Number
n80930hf
Description
Universal Serial Peripheral Controller
Manufacturer
Intel Corporation
Datasheet
1.N80930HF.pdf
(38 pages)
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The 8 x 930H x USB hub peripheral controller is based on the MCS 251 microcontroller. It consists of standard
8XC251Sx peripherals plus a USB module. The USB module provides both USB hub and USB embedded
function capabilities. The 8 x 930H x supports USB hub functionality, embedded function, suspend/resume
modes, isochronous/non-isochronous transfers, and it is fully USB rev 1.0 specification compliant. The USB
module contains one internal and three (or four) external downstream ports and integrates the USB trans-
ceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and
transmit/receive FIFOs. The 8 x 930H x uses the standard instruction set of the MCS 251 architecture, which is
binary code compatible with the MCS 51 architecture.
COPYRIGHT © INTEL CORPORATION, 1997
USB Hub with One Upstream, One
Internal Downstream, and Three
External Downstream Ports on HD/HE
Parts or Four on HF/HG Parts
— Complete Universal Serial Bus Speci-
— Serves as both USB Hub and USB
USB Hub
— Connectivity Management
— Downstream Device
— Power Management, Including
— Bus Fault Detection and Recovery
— Full and Low Speed Downstream
Output Pin for Port Power Switching
Input Pin for Overcurrent Detection
USB Embedded Function
— Supports Isochronous and
On-chip USB Transceivers
Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
— NRZI Encoding/Decoding and
Hub FIFO Data Buffers
— One Pair of 16-byte Transmit and
— One 1-byte Transmit Register
fication 1.0 Compatibility
Embedded Function (Internal Port)
Connect/Disconnect Detection
Suspend and Resume
Device Support
Non-isochronous Data
Bit-stuffing
Receive FIFOs
UNIVERSAL SERIAL BUS HUB
PERIPHERAL CONTROLLER
8 x 930H x
May 1997
Embedded Function FIFO Data Buffers
— Three Pairs of 16-byte Transmit and
— One Pair of Configurable Transmit
Automatic Transmit/Receive FIFO
Management
Three USB Interrupt Vectors
— Endpoint Transmit/Receive Done
— Start of Frame/Hub Endpoint Done
— Global Suspend/Resume
Low Clock Mode
User-selectable Configurations
— External Wait State
— External Address Range
— Page Mode
Real-time Wait Function
256-Kbyte External Code/Data Memory
Space
On-chip ROM Options
— 0, 8, or 16 Kbytes
1024 bytes On-chip Data RAM
Four Input/Output Ports
Standard MCS
Power-saving Idle and Powerdown
Modes
Register-based MCS
Code-compatible with MCS 51 and
MCS 251 Microcontrollers
12-MHz Crystal Operation
Receive FIFOs
and Receive FIFOs (1 Kbyte total)
ADVANCE INFORMATION
®
51 UART
®
Order Number: 272928-003
251 Architecture