n80930hf Intel Corporation, n80930hf Datasheet - Page 16

• Manufacturer Part Number: n80930hf
• Description: Universal Serial Peripheral Controller
• Manufacturer: Intel Corporation

12
8 x 930H x UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
4.0 SIGNALS
A17
A16
A15:8
AD7:0
ALE
AV
CEX2:0
CEX3
CEX4
D
D
D
D
D
M
M
M
M
M
Signal
0
1
2
3
5
Name
CC
, D
, D
, D
, D
, D
P
P
P
P
P
0
1
2
3
5
Type
PWR Analog V
I/O
I/O
I/O
I/O
O
O
O
O
Address Line 17. Output to memory as 18th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
Address Line 16. Output to memory as 17th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
Address Lines. Upper address lines for external memory.
Description is for nonpage mode configuration. For page mode
configuration, data (D7:0) is multiplexed with the upper address
byte (A15:8).
Address/Data Lines. Multiplexed lower address lines and data
lines for external memory. Description is for nonpage mode
configuration. For page mode configuration, data (D7:0) is
multiplexed with the upper address byte (A15:8).
Address Latch Enable. ALE signals the start of an external
bus cycle and indicates that valid address information is
available on lines A15:8 and AD7:0. An external latch can use
ALE to demultiplex the address from the address/data bus.
circuitry.
Programmable Counter Array (PCA) Input/Output Pins.
These are input signals for the PCA capture mode and output
signals for the PCA compare mode and PCA PWM mode.
USB Port 0. D
lines of USB port 0, the upstream differential port. These lines
do not have internal pullup resistors. Provide an external 1.5
K
fullspeed device.
NOTE: D
USB Ports 1, 2, 3, and 5. D
and D
2, 3, and 5, the four downstream differential ports. These lines
have no internal pulldown resistors. Provide an external 15 K
pulldown resistor at each of these pins. (See “Unused
Downstream Ports” on page 33.)
pullup resistor at D
P
5
Table 10. Signal Description (Sheet 1 of 4)
are the data plus and data minus lines of USB ports 1,
causing the 8 x 930H x to stay in reset.
CC
P
. A separate V
0
low and D
P
0
and D
P
M
0
M
0
0
Description
to indicate the connection of a
are the data plus and data minus
CC
low signals an SE0 (USB reset),
P
input for the phase-locked loop
1
, D
P
2
, D
P
3
, D
ADVANCE INFORMATION
M
1
, D
M
2
, D
M
3
, D
M
5,
P1.7/CEX4/WCLK
RD#
P2.7:0
P0.7:0
—
—
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
—
—
Alternate
Function