mc68hc705j2 Freescale Semiconductor, Inc, mc68hc705j2 Datasheet - Page 48

• Manufacturer Part Number: mc68hc705j2
• Description: 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.1.2 External Reset
5.1.3 Computer Operating Properly (COP) Reset
COPR — COP Control Register
RESET
COPR — COP Reset
5.1.4 Illegal Address Reset
MOTOROLA
5-2
COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
A 4064 t cyc (internal clock cycle) delay after the oscillator becomes active
allows the clock generator to stabilize. If the RESET pin is at a logical zero at
the end of 4064 t cyc , the MCU remains in the reset condition until the signal on
the RESET pin goes to a logical one.
A zero applied to the RESET pin for one and one-half t c yc generates an
external reset. A Schmitt trigger senses the logic level at the RESET pin.
A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
timeout period. (See 7.3 COP Timer.) To clear the COP timer and prevent a
COP reset, write a zero to bit 0 (COPR) of the COP control register at location
$0FF0 before the COP timer times out. The COP control register is a write-only
register that returns the contents of an EPROM location when read. See Figure
5-1.
An opcode fetch from an address that is not in the EPROM (locations $0700–
$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
Bit 7
—
—
—
—
6
Figure 5-1. COP Control Register
RESETS AND INTERRUPTS
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
MC68HC705J2
COPR
Bit 0
0
$ 0 F F 0