mc68hc705j2 Freescale Semiconductor, Inc, mc68hc705j2 Datasheet - Page 50

• Manufacturer Part Number: mc68hc705j2
• Description: 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.2.1 Timer Interrupts
5.2.1.1 Timer Overflow Interrupts
5.2.1.2 Real-Time Interrupts
5.2.2 External Interrupt
MOTOROLA
5-4
The return from interrupt (RTI) instruction causes the CPU to recover the CPU
registers from the stack as shown in Figure 5-2.
The timer generates two kinds of interrupts:
Setting the interrupt mask in the condition code register disables timer
interrupts.
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set
while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE
are in the timer control and status register. See 7.2 Timer Control a n d
Status Register.
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set
while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in
the timer control and status register. See 7.2 Timer Control and Status
Register.
When a falling edge occurs on the IRQ pin, an external interrupt request is
latched. When the CPU completes its current instruction, it tests the external
interrupt latch. If the interrupt latch is set and the interrupt mask in the condition
code register is reset, the CPU then begins the interrupt sequence. The CPU
clears the interrupt latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service routine. As
soon as the interrupt mask is cleared (usually during the return from interrupt),
the CPU can recognize the new interrupt request.
Figure 5-3 shows the sequence of events caused by an interrupt.
• Timer overflow interrupt
• Real-time interrupt
RESETS AND INTERRUPTS
MC68HC705J2