mpc8241tzq266c Freescale Semiconductor, Inc, mpc8241tzq266c Datasheet - Page 14

• Manufacturer Part Number: mpc8241tzq266c
• Description: Mpc8241 Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Electrical and Thermal Characteristics
Table 7
conditions (see
4.5.1
Table 8
Section 4.5.2, “Input AC Timing Specifications.”
indicated in
number items listed in
14
At recommended operating conditions (see
Processor frequency (CPU)
Memory bus frequency
PCI input frequency
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
Num
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in
and PCI_SYNC_IN frequencies.
2, 3
5a
5b
8a
8b
10
15
16
17
19
20
1
4
7
provides the operating frequency information for the MPC8241 at recommended operating
Characteristic
provides the clock AC timing specifications at recommended operating conditions, as defined in
Frequency of operation (PCI_SYNC_IN)
PCI_SYNC_IN rise and fall times
PCI_SYNC_IN duty cycle measured at 1.4 V
PCI_SYNC_IN pulse width high measured at 1.4 V
PCI_SYNC_IN pulse width low measured at 1.4 V
PCI_SYNC_IN jitter
PCI_CLK[0:4] skew (pin-to-pin)
SDRAM_CLK[0:3] skew (pin-to-pin)
Internal PLL relock time
DLL lock range with DLL_EXTEND = 0 (disabled) and
normal tap delay; (default DLL mode)
DLL lock range for other modes
Frequency of operation (OSC_IN)
OSC_IN rise and fall times
OSC_IN duty cycle measured at 1.4 V
Clock AC Specifications
Table
Table
4.
Characteristics and Conditions
Figure 6
2) with LV
Table
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
8.
shows the PCI_SYNC_IN input clock timing diagram with the labeled
Table
Min
100
Table 8. Clock AC Timing Specifications
DD
33
166 MHz
= 3.3 V ± 0.3 V.
2) with LV
Table 7. Operating Frequency
Max
166
DD
83
= 3.3 V ± 0.3 V
V
DD
These specifications are for the default driver strengths
/AV
Section 6, “PLL Configuration,”
DD
Min
100
33
/AV
200 MHz
DD
25–66
See
2 = 1.8
Min
Figure 8
25
—
40
—
—
25
—
40
—
—
6
6
Max
200
100
±
See
100 mV
through
Figure 7
Min
100
33
for valid PLL_CFG[0:4] settings
Figure 10
Max
200
250
190
100
2.0
66
60
66
60
9
9
5
266 MHz
Freescale Semiconductor
Max
266
133
MHz
MHz
Unit
ns
ns
ns
ps
ps
ps
µs
ns
ns
ns
%
%
Notes
2, 4, 5
MHz
MHz
MHz
Unit
1
2
2
6
3
6
7