z8l189 ZiLOG Semiconductor, z8l189 Datasheet
z8l189
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z8l189 Summary of contents
Page 1
... V.34 applications), fax, voice messaging, and other communications applications. The Z80189/Z8L189 consists of an enhanced Z8S180 microprocessor, a 16550 MIMIC with increased MIMIC drive capability for direct connection to the IBM PC, XT, AT bus, and 24 bits of parallel I/O. Current PC modem soft- ware compatibility can be maintained with the Z80189's ability to mimic the 16550 UART chip ...
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... GENERAL DESCRIPTION (Continued) Baud Rate Generator 16550 MIMIC Interface COM Decoder PC DMA DMA & I/O Interface Enhanced S180 MPU Figure 1. Z80189 Block Diagram Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 8-Bit Parallel Port A 8-Bit Parallel Port B 8-Bit Parallel ...
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... A8 A9 A10 15 A11 A12 VSS A13 A14 20 A15 A16 A17 A18 VDD 25 A19 Figure 2. Z80189/Z8L189 100-Lead QFP Pin Identification DS971890301 Z80189/Z8L189 100-Pin QFP Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 80 HA0 ...
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... PHI VSS 90 XTAL EXTAL HA4//WAIT HDRQ1//BUSACK /HDACK1//BUSREQ 95 /RESET /NMI /INT0 /INT1/PC6 100 /INT2/PC7 1 Figure 3. Z80189/Z8L189 100-Lead VQFP Pin Identification Z80189/Z8L189 100-Pin VQFP Z80189/Z8L189 ENERAL ...
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... V any condition above those indicated in the operational V +0 sections of these specifications is not implied. Exposure absolute maximum rating conditions for extended periods +150 C may affect device reliability. 100 pF Z80189/Z8L189 ENERAL URPOSE MBEDDED 1 250 A OH Figure 4. Test Load Diagram ...
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... Min Typ Max V –0 2.0 V +0.3 CC –0.3 0.6 –0.3 0.8 2.4 V –0.6 CC 0.40 0.40 2.4 0.4 2.4 0 120 1.8 3 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Unit Condition –200 –200 2 2 mA,** mA,** ...
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... Figure 5. CPU Timing ENERAL URPOSE MBEDDED I/O Write Cycle † I/O Read Cycle † and 26a Z80189/Z8L189 C ONTROLLERS 7 ...
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... Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode [3] [3] Output buffer is off at this point Figure 6. CPU Timing Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS DS971890301 ...
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... Figure 7. CPU Timing CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi [ [3] 17 Figure 8. DMA Control Signals ENERAL URPOSE MBEDDED I/O Write Cycle [ [4] 48 Z80189/Z8L189 C ONTROLLERS 29 9 ...
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... BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode Figure 9. E Clock Timing (Memory Read/Write Cycle I/O Read/Write Cycle) 49 Figure 10. E Clock Timing Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS DS971890301 ...
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... TOUT DS971890301 Figure 11. E Clock Timing (Minimum timing example of PWEL and PWEH) Timer Data Reg = 0000H 55 Figure 12. Timer Output Timing Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...
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... Zilog TIMING DIAGRAMS (Continued) SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT Figure 13. SLEEP Execution Cycle Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Next Opcode Fetch DS971890301 ...
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... Receive Data (External Clock) /MREQ /RAMCS /ROMCS DS971890301 tcyc 58 59 11.5 tcyc 16.5 tcyc 60 61 Figure 14. CSI/O Receive/Transmit Timing 71 Figure 15. /ROMCS and /RAMCS Timing Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS tcyc 58 59 11.5 tcyc 16.5 tcyc ...
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... Figure 17. External Clock Rise Time and Fall Time Address Valid Figure 16. /MWR and /MRD Timing 66 VIH1 VIL1 ENERAL URPOSE MBEDDED Figure 18. Input Rise and Fall Time (Except EXTAL, /RESET) DS971890301 Z80189/Z8L189 C ONTROLLERS 69 ...
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... Delay 37 tBAD2 /PHI to /BUSACK Delay 38 tBZD /PHI to Bus Floating Delay Time 39 tMEWH MREQ Pulse Width (High) 40 tMEWL MREQ Pulse Width (Low) DS971890301 Z8L189-20 MHz Min Max 50 2000 ...
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... If the rise and fall times are greater than the specified maximums, other specifications will not be met. [3] SL1832 is test screened such that specifications 8, 15, and 71 are tested (Tmeol + Tors + Trlcs = 18 ns Z8L189-20 MHz Min Max ...
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... Zilog AC CHARACTERISTICS (Continued) Read/Write External Bus Master Timing Address A7-A0 /IORQ /RD Data /WR Data Figure 19. Read/Write External Bus Master Timing DS971890301 Data In Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 5 Data Out 3 17 ...
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... Delay from /WR THR to Reset HINTR 17 TSTI Delay from MPU /RD of THR to Assert HINTR 18 TIR Delay from /RD to Reset Interrupt Table 1. External Bus Master Timing Z8L189-20 MHz Min Max Table 2. 16550 MIMIC Timing ...
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... Valid Figure 20. PC Host /RD /WR Timing Table 3. PC Host /RD /WR Timing Table Z80L189-20 MHz Min Max Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Z80189-33 MHz Min Max Units ...
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... Hold Valid Figure 21. Com Port Decode Mode PC Host /RD /WR Timing Table 4. Com Port Decode Mode PC Host /RD /WR Timing Table Z8L189-20 MHz Min Max Z80189/Z8L189 ...
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... Fall to Data Out Valid Delay 11 THz /HRD Rise to Data Out Float Delay 12 tRc Read Cycle Delay DS971890301 Valid Valid Z8L189-20 MHz Min Max 30 30 2.5 125 100 2.5 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...
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... HINTR (Line Status RDR /HRD LSR /HRD RBR /HRD /HDDIS 13 Figure 24. Driver Enable Timing Table 6. Driver Enable Timing Table Z8L189-20 MHz Z80189-33 MHz Min Max Min Figure 25. Interrupt Timing RCVR FIFO Z80189/Z8L189 ...
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... RBR or RD LSR) to Reset Interrupt /RD (MPU) TxFIFO HINTR THRE /WR (Host) THR /RD (Host) 11R DS971890301 Table 7. Interrupt Timing RCVR FIFO Table Z8L189-20 MHz Min Max Figure 26. Interrupt Timing Transmitter FIFO Z80189/Z8L189 ENERAL URPOSE ...
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... No Sym Parameter 1 TsPIA(WR) Data Setup Time to (Port) WR Fall 2 TdWR(PIA) Data Valid Delay from WR Rise /WR 1 Port Port (Output Z8L189-20 MHz Min Max 2.5 2 2.5 Table 9. I/O Port Timing Table Z8L189-20 MHz Min Max Port Output Data 1 (Out) Figure 27 ...
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... Read Data Valid Hold from /HRD Inactive 6 tDZ Data Float from /HRD Inactive DS971890301 Table 10. PC DMA Mailbox Timing Z8L189-20 MHz Min Max 144 301 454 133 25 Table 11. PC DMA Mailbox Timing Z8L189-20 MHz Min ...
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... The HDRQ will not fall inactive until it sees the falling edge of /HRD during the /HDACK cycle Figure 29. PC DMA Read: I/O-Read, Memory-Write DMA Bus Cycle Bus DMA Bus Cycle Bus Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ( ...
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... These pins may be programmed to provide active low level, rising or falling edge interrupts. The level of the external /INT1 and /INT2 pins may be read through bits PC6 and PC7 of parallel port C. Z80189/Z8L189 ENERAL ...
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... COM Port Decoder. When setting the /HCS Force bit in the CDR register, the /HCS output is asserted when HA3-HA9 is within the boundaries pro- grammed by bits 3-4 of the CDR register and /HRD or /HWR is asserted. /HCS is NOT asserted for PC DMA Mailbox accesses. Z80189/Z8L189 ENERAL ...
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... XX80 to XXBF for I/O transactions. A15 through A8 are not decoded so that the chip select is active in all pages of I/O address space. The /IOCS1 function is the default on power on or reset condition and is changed by programming bit 2 in the Interrupt Edge/Pin Mux Register. Z80189/Z8L189 ENERAL ...
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... These pins are selected such that they are all high-z inputs at power up to prevent any problems with connecting address lines directly to PC bus. Although, the COM decode multiplexing is enabled on power-up, the COM address decoding is disabled. Z80189/Z8L189 ENERAL URPOSE ...
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... DS971890301 Table 12. Z80189 Pin-Out DEFAULT SECONDARY FUNCTION FUNCTION A10 A11 A12 V SS A13 A14 A15 A16 A17 A18 V DD A19 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS CONTROL 31 ...
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... HD1 PA1 HD2 PA2 HD3 PA3 HD4 PA4 HD5 PA5 HD6 PA6 HD7 PA7 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS CONTROL System Config Reg bit 5 System Config Reg bit 5 System Config Reg bit 5 System Config Reg bit 5 System Config Reg bit 5 ...
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... Central Processing Unit. The CPU is microcoded to provide a core that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply. This core has been modified to allow many of the instructions to execute in fewer clock cycles. Z80189/Z8L189 ENERAL ...
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... Z189 or any measurement device connected to the inputs. The auto latch will latch onto the previous state of input pin. 4. Pin simultaneously acts as input for both default and secondary functions. 5. /WAIT is pulled high internally when default function is active. 6. Upon power-up or reset, this pin is tri-state. Z80189/Z8L189 ENERAL ...
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... CKS MMU A19-A0 DS971890301 Bus State Control CPU DMACs (2) Asynchronous SCI (Channel 0) Asynchronous SCI (Channel 1) D7-D0 Figure 30. Z189 MPU Block Diagram Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Interrupt /DREQ1 /TEND0 TxA0 CKA0/ /DREQ0 RxA0 /RTS0 /CTS0 ...
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... If DCD is not auto-enabled, the /DCD pin has no effect on the FIFOs or enable bits. Error Latches 4x4 Bit Error MP 4-Byte FIFO Bit Data FIFO Error Shift Register Figure 31. ASCI Receiver Z80189/Z8L189 ENERAL URPOSE MBEDDED DAR18-16 Destination 000 ext (CKA0//DREQ0) 001 ASCI0 Tx 010 ASCI1 Tx 011 ...
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... FIFO is full and the break occurs the MP bit in the transmission is not a 1 with the conditions specified above. Parity and Framing Errors Parity and Framing Errors do not affect subsequent re- ceiver operation. Z80189/Z8L189 ENERAL ...
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... The T output of PRT1 is available on a multiplexed pin. OUT Clocked Serial I/O (CSIO) The CSI0 channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high- speed data connection to another microprocessor or microcomputer. Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...
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... OSC. CLKOUT Source Running Running RESET, Interrupts Running Running By Programming Running Running RESET, Interrupts Running Stop RESET, Interrupts, BUSREQ Stop Stop RESET, Interrupts, BUSREQ Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Recovery Time (Minimum) 1.5 Clock - 1.5 Clock 8 +1.5 Clock 2 17 +1.5 Clock (Normal Recovery) ...
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... If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the /BUSREQ would not cause the Z8S180 to exit STANDBY mode. If STANDBY mode is exited due to a reset or an external interrupt, the Z8S180 remains relinquished from the sys- tem bus as long as /BUSREQ is active. Z80189/Z8L189 ENERAL ...
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... RESET, BUS REQUEST or EXTERNAL INTERRUPTS; the clock and other control signals are recovered sooner than the STANDBY mode. Note: If STANDBY-QUICK RECOVERY is enabled, the user must make sure stable oscillation is obtained within 64 clock cycles. Z80189/Z8L189 ENERAL ...
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... R/W Refresh Control Register %0018/58/98 R/W MMU Common Base Register MMU Bank Base Register %001A/5A/9A R/W MMU Common/Bank Area Register %003A/7A/BA R/W %001B/5B/9B R/W %001C/5C/9C R/W Operation Mode Control Register I/O Control Register %001D/5D/9D RW %001E/5E/9E RW Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS I/O Addr/Access %001F/5F/9F R/W %0020/60/A0 R/W %0021/61/A1 R/W %0022/62/A2 R/W ...
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... Start + 7-Bit Data + Parity + 2 Stop 0 Start + 8-Bit Data + 1 Stop 1 Start + 8-Bit Data + 2 Stop 0 Start + 8-Bit Data + Parity + 1 Stop 1 Start + 8-Bit Data + Parity + 2 Stop Read - Multiprocessor Bit Receive Write - Error Flag Reset CKA1 Disable Transmit Enable Receive Enable Multiprocessor Enable Z80189/Z8L189 C ONTROLLERS 43 ...
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... Multiprocessor Bit Transmit (Divide Ratio = 30 (x16 (x64) Ø 480 Ø Ø 960 Ø Ø 1920 Ø Ø 3840 Ø Ø 7680 Ø Ø 15360 Ø Ø 30720 Ø DS971890301 Z80189/Z8L189 C ONTROLLERS 1920 3840 7680 15360 30720 61440 122880 ...
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... Figure 35. ASCI Control Register B (Ch. 1) Z80189/Z8L189 ENERAL URPOSE MBEDDED 1 Clock Source and Speed Select Divide Ratio Parity Even or Odd Read - Status of /CTS pin Write - Select PS Multiprocessor Multiprocessor Bit Transmit ...
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... Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full TIE 0 R/W Transmit Interrupt Enable Transmit Data Register Empty /CTS1 Enable Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full DS971890301 Z80189/Z8L189 C ONTROLLERS ...
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... Figure 42. ASCI0 Extension Control Register Figure 43. ASCI1 Extension Control Register Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 0 New Z8S180 Register 0 Send Break 0 = Normal Xmit 1 = Drive TXA Low Break Detect (RO) Break Feature Enable ...
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... Bit 0-6. Reserved. Maintains a logic 1 value when read Reserved X2 Clock Multiplier Mode 0 = Disable 1 = Enable Figure 44. Clock Multiplier Register (Z180 MPU Address 1EH) Z80189/Z8L189 ENERAL URPOSE MBEDDED ASCI1 Time Constant Low 1Ch ASCI1 Time Constant High ...
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... Figure 45. CSI/O Control Register Addr 0BH Read - Received Data Write - Transmit Data Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS SS0 1 R/W Speed Select Transmit Enable Receive Enable End Interrupt Enable End Flag Baud Rate Ø ...
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... When Read, read Data Register L before reading Data Register H. Figure 50. Timer 1 Data Register H RLDR0H Read/Write Figure 53. Timer 0 Reload Register H RLDR1H Read/Write Figure 54. Timer 1 Reload Register H Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Addr 0DH 8 Addr 15H 8 ...
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... Addr 10H TIE1 TIE0 TOC1 TOC0 TDE1 TDE0 R/W R/W R/W R/W R/W T oggle 0 1 Figure 55. Timer Control Register ENERAL URPOSE MBEDDED 0 R/W Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0 Z80189/Z8L189 C ONTROLLERS 51 ...
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... EMI noise generated by the part. CPU Control Register (CCR) Addr 1FH Figure 57. CPU Control Register Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS LNAD/ Standard Drive 1 = 33% Drive On A19-A0, D7-D0 ...
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... E Bit 0. LNAD/DATA. This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus output is reduced to 33% of its original drive capability. Z80189/Z8L189 ENERAL URPOSE MBEDDED ...
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... Read/Write BC7 BCR0H Read/Write BC15 Figure 60. DMA 0 Byte Counter Registers MAR1L Read/Write MA7 MAR1H Read/Write MA15 MAR1B Read/Write - Figure 61. DMA 1 Memory Address Registers Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS Addr 26H BC0 Addr 27H BC8 Addr 28H MA0 Addr 29H ...
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... Currently selected DMA Channel when Bit Alternating Channels Figure 64. DMA I/O Address Register Ch ENERAL URPOSE MBEDDED BCR1L Read/Write Addr 2EH BC7 BC0 BCR1H Read/Write Addr 2FH BC15 BC8 0 = DMA Channels are independent 1 = Toggle between DMA channels for same device Z80189/Z8L189 C ONTROLLERS 55 ...
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... Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS /DREQ1 ASCI0 Tx ASCI1 Tx ext CKA0//DREQ0 Reserved, do not program. Reserved, do not program. Reserved, do not program ext /DREQ1 ASCI0 Rx ASCI1 Rx ext CKA0//DREQ0 Reserved, do not program. ...
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... R DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Addr 31H - 0 1 R/W Memory MODE Select Ch 0 Source Mode Destination Mode 1, 0 Source Address M SAR0+1 M SAR0-1 M SAR0 Fixed I/O SAR0 Fixed Z80189/Z8L189 C ONTROLLERS 57 ...
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... Sense Edge Sense Level Sense Transfer Mode Address Increment/Decrement M - I/O MAR1 I/O MAR1-1 I IAR1 Fixed I IAR1 Fixed Figure 67. DMA/WAIT Control Register Z80189/Z8L189 ENERAL URPOSE MBEDDED Addr 32H DIM0 0 R/W DMA Ch 1 I/O Memory Mode Select /DREQi Select I/0 Wait Insertion Memory Wait Insertion ...
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... R/W R/W Figure 69. INT/TRAP Control Register - - - - CYC1 CYC0 R/W Interval of Refresh Cycle 10 states 20 states 40 states 80 states Figure 70. Refresh Control Register Z80189/Z8L189 ENERAL URPOSE MBEDDED Addr 33H - - 0 0 Interrupt Vector Low Addr 34H ITE0 1 R/W /INT Enable Undefined Fetch Object TRAP Addr 36H ...
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... R/W R/W R/W R/W R/W Figure 72. MMU Bank Base Register CA1 CA0 BA3 BA2 BA1 R/W R/W R/W R/W R/W Z80189/Z8L189 ENERAL URPOSE MBEDDED Addr 38H CB0 0 R/W MMU Common Base Register Addr 39H BB0 0 R/W MMU Bank Base Register Addr 3AH BA0 0 R/W MMU Bank Area Register MMU Common Area Register ...
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... W R don't care part of Initialization. fetch a RETI instruction. Figure 74. Operation Mode Control Register Addr 3FH - - - - IOSTP R/W R/W Figure 75. I/O Control Register ENERAL URPOSE MBEDDED - 1 I/O Compatibility /M1 T emporary Enable /M1 Enable - 1 I/O Stop I/O Address Combination reserved Z80189/Z8L189 C ONTROLLERS 61 ...
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... W only MPU Addr/Access XXEDH R/W XXEEH R/W XXE9 W only XXE8 R/W XXE7 R/W XXE6 R/W XXE5 R/W XXE4 R/W XXE1 R/W XXE0 R/W XXDF R/W XXDE R/W XXDD R/W XXD9 R/W XXD8 R/W XXD6 R/W XXD7 R/W XXEF R/W Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS PCAddr/Access None None None None None None None None None None ...
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... Note: All register addresses not listed are Reserved. DS971890301 MPU Addr/Access %XXD5 W bit 1/R %XXD4 R %XXD4 W %XXD3 R %XXD2 R/W %XXD1 R %XXD1 W %XXD0 R (1) %XXD0 W Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS PC Addr/Access Prog + 10b R (2) Prog + 01b W (2) Prog + 01b R (2) ...
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... COM Port Decode 4 8 16550 MIMIC Register Set Host IRQ DMA Mailbox and I/O Mailbox Figure 76. 16550 MIMIC Block Description Z80189/Z8L189 ENERAL URPOSE MBEDDED 180 Side Rx Timer Z80180 Tx Timer Address Control Config Register Z80180 IRQ & ...
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... Timer, which is an additional 8 bit timer with BRG as the input source. If the transmitter FIFO is non-empty and no PC write or MPU read of the FIFO has taken place within the timer interval, a time-out will occur causing a correspond- ing interrupt to the MPU. Z80189/Z8L189 ENERAL ...
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... MPU F Databus E (MPU Side Write) R phi MPU IRQ MPU Side Interface 16x8 Data Bits I Write ALU Pointer Figure 77. Receiver FIFO Block Diagram Z80189/Z8L189 ENERAL URPOSE MBEDDED error PC Read 3 LSR B2-B4 R phi 16x3 E Error A Bits D Sync ...
Page 67
... Write ALU Pointer Pointer Figure 78. Transmitter FIFO Block Diagram ENERAL URPOSE MBEDDED phi R E Sync Read Z80189/Z8L189 C ONTROLLERS MPU_RD MPU Read (Data) FCR Reg. MPU IRQ 16550 MIMIC or PC Side Interface 67 ...
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... MPU writes 1 MPU writes 1 MPU writes 1 MPU makes two writes to receiver buffer register MPU writes to RCVR FIFO or receiver buffer register Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS How to Clear When there are no more errors MPU writes a 0 ...
Page 69
... If character delay emulation is not used the TEMT bit in the LSR Register is set whenever both the THR Register and the TSR buffer are both empty. The Host TEMT bit is clear if there is data in either the TSR buffer or THR Register. Disable this feature when 16550 FIFO mode is enabled. Z80189/Z8L189 ...
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... Shift Reg. Added TSR Buffer for the 0 Emulation transmit data Z80189 MIMIC Design Hint The MIMIC output drive capability has been increased the Z189. This may eliminate the need for buffering to the PC Bus. Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...
Page 71
... Both bits should never be set to one. This is a reserved condition and should not be used. Bit 0 Vector Include Status (Read/Write) This bit is used to select the interrupt response mode of the Z180 this bit enables mode 0 interrupts enables mode 2 response. Z80189/Z8L189 ENERAL ...
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... MS locations and then repoll this bit. If only one location is interrupting, the interrupt will be cleared when that location is read by the Z180. Bit 0 FIFO Control Register Write (Read Only) This bit is set when the PC/XT/AT writes to the FCR reset when the Z180 MPU reads this register. Z80189/Z8L189 ENERAL ...
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... These three bits are the Interrupt Status bits when VIS in the MMC register is a one. If the VIS bit is a zero, then these bits contain what was last written to them. Bits 321 000 001 010 011 100 101 110 111 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 0/Opcode ...
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... This will prevent an RTO from occurring before a (delayed) receiver trigger level interrupt. When cleared, the RTO will begin timeout from the last read or write to the receiver FIFO. Z80189/Z8L189 ENERAL URPOSE MBEDDED ...
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... PC will not see data requests from an empty FIFO any faster than would occur with a true UART when the delay feature is enabled. This timer is also used to delay data transfer from THR Register to Z80189 TSR buffer in double buffer mode. Z80189/Z8L189 ENERAL ...
Page 76
... Receiver Buffer Register. In FIFO mode, this address is used to read (PC) and write (Z180) the Receiver FIFO Read Only, (Address 00h, DLAB=0, R/W=Read) (Z180 MPU Write Only, Address xxF0H) Figure 89. Receiver Buffer Register Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...
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... FIFO mode. This bit must when writing to the other bits in this register or they will not be programmed. When this bit changes state, any data in the FIFO’s or transmitter holding and receiver buffer registers is lost and any pend- ing interrupts are cleared. Z80189/Z8L189 ...
Page 78
... Overrun, Parity, Framing error or Break detect bits set by MPU. Received Data trigger level Receiver Time-out with data in RCVR FIFO. Transmitter Holding Register Empty. MODEM status: CTS,DSR,RI or DCD. Z80189/Z8L189 ENERAL URPOSE MBEDDED Interrupt Pending ...
Page 79
... Interrupt Enable Register PC/XT/AT Read/Write, PC Address 01H Z180 MPU Read Only, Z180 MPU Address XXF1H Figure 95. Interrupt Enable Register Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 0 0 Bit 0 Received Data Available Int. Bit 1 THRE Interrupt Bit 2 Receiver Line Status Int ...
Page 80
... MIMIC Master Control Register are a 10. Or else it can be read by the Z180 MPU. Bit 2-Bit 0 These bits have no direct control of the 16550 MIMIC interface and the Z180 MPU must emulate the function implemented. Z80189/Z8L189 ENERAL ...
Page 81
... Bit 7-0 Divisor Latch Most Significant (MS) This register contains the high order byte of the Baud rate divisor. Writing to this register with the PC/XT/AT will generate an interrupt to the Z180 MPU. It can then read the Baud rate divisor and set up application. Z80189/Z8L189 ENERAL ...
Page 82
... HDRQ1 will be tri-stated. When the HDMAE0 bit is set the HDRQ0 output will become fully driven, otherwise, the HDRQ0 output will be tri-stated. I/O address XXD2h is assigned the HMC register. Bits 0 and 1 of the HMC register are respectively assigned HDMAE0 and HDMAE1. Z80189/Z8L189 ENERAL ...
Page 83
... DMA request. The Z180 clears HDREQ and sets HDMAE, forcing HDRQ low. The PC DMA Read proceeds as follows: 1. Z180 software outputs the data byte to HDMAR, where it is latched. 2. Z180 software writes the HDREQ bit, causing the HDRQ pin to go active high. Z80189/Z8L189 ENERAL URPOSE ...
Page 84
... QFP pins as shown below: HDRQ, pin 50, output (mux with RTS0) /HDACK0, pin 43, input (mux with CKA0 and /DREQ0) HDRQ1, pin 97, output (mux with /BUSACK) /HDACK1, pin 98, input (mux with /BUSREQ) Z80189/Z8L189 ENERAL URPOSE ...
Page 85
... MAILBOX DATA. Bit 0 HDMAE0 bit When this bit is set allows Mailbox 0 to request a PC DMA cycle given that the Mailbox 0 pins are multiplexed (bit 4=1). When this bit is cleared to 0, the HDREQ0 is tri- stated if Mailbox 0 pins are multiplexed. Z80189/Z8L189 ENERAL ...
Page 86
... Modem to a COM Port and interrupt such that there are no resource conflicts. In order to facilitate the feature listed above, a communica- tion path needs to be available between a PC BIOS and Modem PRIOR to the selection of COM Port, DMA, or IRQ selection. Z80189/Z8L189 ENERAL ...
Page 87
... Bit 1. Host Output Register 0 Data Available. This bit 0 0 becomes set when the PC Host writes to the Host Output Register 0. A Z180 read of the Host Output Register 0 will cause this bit to clear. This bit cannot be set unless the Host I/O Mailbox enable bit is set. Z80189/Z8L189 ENERAL URPOSE ...
Page 88
... S180 core. The time constant required for a specific bit rate is as follows: Time constant (decimal) = (PHI freq. / (2*baud rate))-2 This formula is exactly the same as used in the ESCC. The output of the BRG is directly connected to MIMIC emulation counter input. Z80189/Z8L189 ENERAL URPOSE ...
Page 89
... Note: When waking from Standby Mode using a PC-THR write, the THRE bit will not reset until clock is stabilized. This may cause a THR overrun. Therefore, data integrity cannot be guaranteed. Care should be taken so that standby mode is only used when data integrity is not essential. Z80189/Z8L189 ENERAL URPOSE ...
Page 90
... Therefore, MIMIC access is disabled until the first System Configuration Register Write on COM Decode (bit 5) is enabled. This mechanism prevents accidental bus con- tention if /HCS/HC1 pin is pulled low. Note: The COM Decode Register must be written first, prior to the System Configuration Register during initializa- tion. Z80189/Z8L189 ENERAL URPOSE MBEDDED HA2-HA0 are used to select between internal MIMIC registers ...
Page 91
... In this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions outside the Z80189. This allows the use of ROM emulators/logic analyzers for application develop- ment. See Figures 115 and 116. Z80189/Z8L189 ENERAL ...
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... Low. To avoid accidental conten- tion when /HCS/HC1 is pulled low advisable that the COM Decode Register is written first prior to when the system configuration register is initialized. . When this OUT Z80189/Z8L189 ENERAL URPOSE ...
Page 93
... Figure 117. Data Bus Direction (Z80180 is Not Bus Master) DS971890301 I/O Write I/O Read to Off-Chip from Off-Chip Peripherals Peripherals Out Z Z Out Z Z Intack for Off-Chip In In Z80189/Z8L189 ENERAL URPOSE MBEDDED Write to Write from Z80189 Memory Memory Refresh Idle Mode ...
Page 94
... This signal can be forced to a "1" (inactive state) by setting Bit 3 in the System Configuration Register, to allow the user to overlay the RAM area over the ROM area Figure 120. ROMBR (Z180 Address xxE8H) Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS A19-A12 ROMBR ...
Page 95
... DCNTL do not add. The actual number of wait states inserted is the greater of the two. DS971890301 Figure 121. WSG Chip Select Register (Z180 MPU Read/Write, Address XXD8H) Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 0 /ROMCS Wait States ...
Page 96
... By programming this bit to ‘1’, low noise for the Z189 pins is chosen (not the Z180 pins). Programming this bit to ‘0’ selects normal drive for the Z189 pins. Z189 pins include: all MIMIC output pins, ROM/RAM chip selects, bit I/O, IOCS1, IOCS2, and PC DMA Mailbox outputs. Z80189/Z8L189 ...
Page 97
... PHI output, this feature can be used to reduce EMI. When this bit is reset, the system clock is output to PHI pin. This bit is reset by default. This feature is not usable in EV mode 1 (emulation adapter mode 2 (emulation probe). Z80189/Z8L189 ENERAL ...
Page 98
... Figure 124. PA Data Direction Register The data direction register determines which are inputs and outputs in the PA Data Register. When a bit is set to a one, the corresponding bit in the PA Data Register is an input. If the bit is zero, then the corresponding bit is an output. Z80189/Z8L189 ENERAL ...
Page 99
... When operating either /INT2 or /INT1 in edge detection mode, the edge detect latch is reset by writing a '1' to bit respectively. Writing a '0' has no effect. These latches should be reset at the end of an /INT1 or /INT2 interrupts service routine when using edge-triggered interrupt routine. Z80189/Z8L189 ENERAL ...
Page 100
... This scheme allows a Z189 emulator probe to grab onto the Z189 package leads on the target system. Mode 3 Description Reserved for Test Mode. Note also that in Mode 1 and 3, the emulator must provide /MREQ on the (/MREQ) Z80189 pin. Z80189/Z8L189 ENERAL URPOSE ...
Page 101
... A0-A19 is always high-Z in power down. D0-D7 always high-Z in power down modes. HDRQ0, HDRQ1 are high-Z in HALT or Sleep. RS, equivalent resistance: 60 Ohms 15~22 pF. IN OUT XTAL Crystal Inputs EXTAL Figure 130. Circuit Configuration for Crystal Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS C1 C2 101 ...
Page 102
... =2 =200 3.3V DD fined. Unused pins need not be pulled up or pulled down to prevent ESD or power drain. Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS DS971890301 ...
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... HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 PC5 PC3 PC2 PC1 PC0 PC4 "input" or "output" column indicates the pin does not have that function. Z80189/Z8L189 ENERAL URPOSE MBEDDED SECONDARY FUNCTION TXS /CTSO /DCD0 TXA0 RXA0 TXA1 RXA1 RXS//CTS1 ...
Page 104
... TXA0 HA0 HA1 RXA0 HA2 /HCS HC1 /HALT HA3 /RFSH /IORQ /MREQ MRD /IOCS2 E /M1 /WR /RD PHI XTAL EXTAL HA4 /WAIT HDRQ1 /BUSACK /HDACK1 /BUSREQ /RESET /NMI /INTO /INT1 PC6 /INT2 PC7 Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS DS971890301 ...
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... Zilog PACKAGE INFORMATION DS971890301 100-Lead QFP Package Diagram Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS 105 ...
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... Zilog PACKAGE INFORMATION (Continued) 106 100-VQFP Package Diagram Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS DS971890301 ...
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... Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com Z80189/Z8L189 ENERAL URPOSE MBEDDED ONTROLLERS ...