z8l189 ZiLOG Semiconductor, z8l189 Datasheet - Page 89

• Manufacturer Part Number: z8l189
• Description: General-purpose Embedded Controllers
• Manufacturer: ZiLOG Semiconductor

DS971890301
Baud Rate Generator Register
The following registers are used to store BRG constant.
The timer is enabled after setting bit 0 of IOBRG register.
Design is such that on-the-fly modification of registers do
not cause irregular BRG output.
IOBRG Register
The following register handles the IOCS feature and MIMIC
BRG. IOBRG-IOCS & BRG enable (Address XXD6H)
Default 04 hex.
Bits 4-7 Reserved
Bit 3
R/W
Zilog
7
0
Figure 111. BRGL Baud Rate Generator Low
6 5
0 0
7
1
Figure 113. IOBRG-IOCS and BRG Enable
/INT0 assertion on MIMIC access. When this bit
is enabled, and the /HALT is active (power-down)
any HOST access to the MIMIC will cause a low
edge. Since this interrupt source has no vector,
/INT0 MODE 1 must be used when enabling this
mode. This is disabled on power-up. /INT0 asser-
tion is released when /HALT is deasserted.
6 5
1
(Address XXE0H) Default 00 Hex
4
0
1 1
3 2 1
0
4
1 0
3 2 1
1 1
(Address XXD6H)
1
0
0
0
1
BRG Enable
/IOCS2 Range
/IOCS2 Enable
/INTO Assertion of
Reserved as 0
MIMIC Access
1 = I/O Access between
0 = I/O Access between
Time Constant
Lower Byte of
xxC0h-xxC7
xxC8h-xxCF
P R E L I M I N A R Y
Note: The THRE bit is forced to 0 on the PC side to prevent
THR overrun during powerdown modes when this feature
is enabled. When the MIMIC comes out of power-down,
THRE resumes normal functionality.
Bit 2
Bit 1
R/W
Bit 0
R/W
Note: When waking from Standby Mode using a PC-THR
write, the THRE bit will not reset until clock is stabilized.
This may cause a THR overrun. Therefore, data integrity
cannot be guaranteed. Care should be taken so that
standby mode is only used when data integrity is not
essential.
Figure 112. BRGH Baud Rate Generator High
7
1
/IOCS2 enable
When set, IOCS2 is muxed over E pin. This is
enabled on reset.
/IOCS2 range.
When set, IOCS2 is active during I/O accesses
between XXC0H-XXC7H.
When reset, IOCS2 is active during I/O accesses
between XXC8H-XXCFH. This is disabled on
power-up.
BRG enable. When set,
the MIMIC BRG begins counting down to gener-
ate a programmed square wave to the MIMIC
emulation timers. This is disabled on power-up.
6 5
1
(Address XXE9H) Default 00 Hex
1 1
4
3 2 1
1 1
G
1
ENERAL
0
1
-P
URPOSE
Time Constant
Upper Byte of
E
MBEDDED
Z80189/Z8L189
C
ONTROLLERS
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