z8l189 ZiLOG Semiconductor, z8l189 Datasheet - Page 81

• Manufacturer Part Number: z8l189
• Description: General-purpose Embedded Controllers
• Manufacturer: ZiLOG Semiconductor

DS971890301
Modem Status Register
Bit 7 Data Carrier Detect
This bit must be written by the Z180 MPU.
Bit 6 Ring Indicator
This bit must be written by the Z180 MPU.
Bit 5 Data Set Ready
This bit must be written by the Z180 MPU.
Bit 4 Clear to Send
This bit must be written by the Z180 MPU.
Bit 3 Delta Data Carrier Detect
This bit is set to a one whenever the Data Carrier Detect bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 2 Trailing Edge Ring Indicator
This bit is set to a one on the falling edge of the Ring
Indicator bit. This bit is reset when the PC/XT/AT reads the
Modem Status Register.
Bit 1 Delta Data Set Ready
This bit is set to a one whenever the Data Set Ready bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 0 Delta Clear To Send
This bit is set to a one whenever the Clear To Send bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Zilog
PC/XT/AT Read Only, PC/XT/AT Address 6H
Z180 MPU Read/Write Bits 7-4, Z180 MPU Address XXF6H
7
0
6 5
0 0
Figure 98. Modem Status Register
4
0
0
3 2 1
0 0
0
0
DCTS
DDSR
TERI
DDCD
CTS
DSR
RI
DCD
P R E L I M I N A R Y
Scratch Register
Bits 7-0 Scratch Register
This register is used by the PC/XT/AT programmer for
temporary data storage. The Z180 MPU is able to read this
register. If the PC/XT/AT writes to this register, no interrupt
to the Z180 MPU is generated.
Divisor Latch (LS)
Bit 7-0 Divisor Latch Most Significant (MS)
This register contains the low order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
Divisor Latch (MS)
Bit 7-0 Divisor Latch Most Significant (MS)
This register contains the high order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up application.
PC/XT/AT Read/Write, PC/XT/AT Address 01H and DLAB = 1
Z180 MPU Read Only, Z180 MPU Address XXF9H
7
X X X X X X X X
PC/XT/AT Read/Write, PC/XT/AT Address 00H and DLAB = 1
Z180 MPU Read Only, Z180 MPU Address XXF8H
PC/XT/AT Read/Write, PC/XT/AT Address 07H
Z180 MPU Read Only, Z180 MPU Address XXF7H
7
X X X X X X X X
7
X X X X X X X X
6 5
6 5
6 5
4
Figure 101. Divisor Latch (MS)
Figure 100. Divisor Latch (LS)
4
4
Figure 99. Scratch Register
3 2 1
3 2 1
3 2 1
0
G
0
0
ENERAL
Divisor Latch (MS)
Scratch Register
Divisor Latch (LS)
-P
URPOSE
E
MBEDDED
Z80189/Z8L189
C
ONTROLLERS
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