z8l189 ZiLOG Semiconductor, z8l189 Datasheet - Page 73

• Manufacturer Part Number: z8l189
• Description: General-purpose Embedded Controllers
• Manufacturer: ZiLOG Semiconductor

DS971890301
Interrupt Enable Register
The IE Register allows each of the 16550/8250 interrupts to
the Z180 MPU to be masked off individually or globally.
Bit 7 Master Interrupt Enable (Read/Write)
If bit 7 is a zero, all interrupts from the 16550 MIMIC are
masked off. If this bit is a one, then Interrupts are enabled
individually by setting the appropriate bit.
Bit 6 Enable THR Interrupt (Read/Write)
If this bit is a one, it enables the Transmitter Holding
Register Interrupt.
Bit 5 Enable TTO Interrupt (Read/Write)
If this bit is a one, it enables the Transmitter Time-out
Interrupt. This will interrupt the CPU when characters
remain in the FIFO below the trigger level and the FIFO is
not read or written for the length of time in the transmitter
time-out register.
Bit 4 Enable RBR Interrupt (Read/Write)
If this bit is a one, it enables the Receiver Buffer Register
Interrupt.
Bit 3 Enable MCR Interrupt (Read/Write)
If this bit is 1, it enables the Modem Control Register
Interrupt
Bit 2 Enable LCR Interrupt (Read/Write)
If this bit is a one, it enables the Line Control Register
interrupt.
Bit 1 Enable DLL/DLM Interrupt (Read/Write)
If this bit is 1, it enables the Divisor Latch least and Most
Significant Byte Interrupts
Bit 0 Enable FCR Interrupt (Read/Write)
If this bit is a one, then interrupts are enabled for a PC write
to the FIFO control register (FCR).
Zilog
7
0
6 5
0 0
4
0
(Z180 MPU Address XXFDH)
0
3 2 1
Figure 82. IE Register
0 0
0
0
Interrupt Enable
MIE
6 Enable THR IRQ
5 Enable TTO IRQ
4 Enable RBR IRQ
3 Enable MCR IRQ
2 Enable LCR IRQ
1 Enable DLL/DLM IRQ
0 Enable FCR IRQ
P R E L I M I N A R Y
Priority of interrupts are in this order:
Highest 6. THR IRQ
Lowest 0. FCR IRQ
Interrupt Vector Register
The Interrupt Vector Register contains either the opcode or
the Lower Address for a Z180 interrupt, depending upon
the VIS bit in the MMC Register. If the VIS bit is a zero, then
Z180 Mode 0 interrupt is selected, if the VIS bit is a one then
Z180 Mode 2 is selected.
Bit 7-4 Upper Nibble IVEC (Read/Write)
These four bits are to generate either an opcode or the
upper four bits of the eight bit address to support the Z180
interrupt modes. These bits are read/write and always read
back what was last written to them.
Bits 3-1 Status/Opcode (Read/Write)
These three bits are the Interrupt Status bits when VIS in the
MMC register is a one. If the VIS bit is a zero, then these bits
contain what was last written to them.
7
0
6 5
0 0
5. TTO IRQ
4. RBR IRQ
3. MCR IRQ
2. LCR IRQ
1. DLL IRQ
1. DLM IRQ
Bits
0
4
(Z180 MPU Address XXFCH)
Figure 83. IVEC Register
3 2 1
0
321
000
001
010
011
100
101
110
111
0 0
NO IRQ
FCR IRQ
DLL/DLM IRQ
LCR IRQ
MCR IRQ
RBR IRQ
TTO IRQ
THR IRQ
G
0
0
ENERAL
-P
0/Opcode
Status/Opcode
Upper Nibble IVEC
URPOSE
E
MBEDDED
Z80189/Z8L189
C
ONTROLLERS
73