lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 118

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Note 1: The GPIO Data and Configuration Registers are located in PME block at the offset shown from the
RUNTIME REGISTERS BLOCK address.
6.12.3 GPIO CONTROL
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the
“Runtime Registers” section or the “Configuration Registers” section in Logical Device A of this specification.
Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be
programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of
each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7]
determines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO
functions and the nSMI Alternate functions.
The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the GPIO
function and when the pin is configured for the alternate function for all pins, with the exception of the DDRC function
on GP43 and the either edge triggered interrupts.
SMSC LPC47S45x
PIN NO.
/QFP
100
101
102
103
N/A
N/A
N/A
N/A
N/A
107
108
109
110
111
112
113
114
97
98
99
51
52
43
35
36
37
38
39
40
41
42
FUNCTION
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULT
nXCS0
nXWR
nXRD
XCS1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
XA0
XA1
XA2
XA3
Data Set Ready 2
Request to Send
Clear to Send 2
Transmit Serial
Receive Serial
Date Terminal
FUNCTION 1
Data Carrier
Detect 2
Ready 2
IRQINC
Data 2
Data 2
LED1
LED2
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT.
2
DATASHEET
FUNCTION 2
Infrared Rx
Infrared Tx
Page 118 of 259
EETI
EETI
ALT.
FUNCTION 3
ALT.
REGISTER
DATA
GP6
GP7
GP8
1
DATA REG
BIT NO.
4
3
4
5
6
1
6
1
2
3
5
6
7
0
1
2
7
0
2
3
4
5
7
0
1
2
3
4
5
6
7
Rev. 08-10-09
OFFSET
(HEX)
REG
4A
50
51