lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 98

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Note:
Note 1: The polarity of IRQ8 is programmable via bit 0 of register 0xF1 in Logical Device A.
6.9.2
Each bank has a CMOS Address Register and a CMOS Data Register. Each bank’s CMOS Address Register is
located at the corresponding base address setup by the Configuration Registers in Table 45. Each bank’s CMOS
Data Register is located at an offset of the corresponding base (see Table 46.)
Registers is not used for the CMOS RAM address decoding. All four CMOS Run Time registers are fully read/write.
Note 1: CMOS Address Register for Bank0 is a write only register at this address. The contents of this register are readable
in the configuration register section. (see Table 45 − RTC CONFIGURATION R)
6.9.3
Table 47 shows the address map of the RTC and CMOS RAM, eleven registers of time, calendar, century, and alarm
data, four control and status registers, and 241 bytes of CMOS registers
SMSC DS – LPC47S45x
0xF1
INDEX
0xF0
This is a read/write bit that is ignored.
HOST I/O INTERFACE
INTERNAL REGISTERS
R
TYPE
R/W
HOST ADDRESS*
Bank0 * (W) (note 1)
Bank0 * + 1(R/W)
Bank1 * (R/W)
Bank1 * + 1(R/W)
-
BANK
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
Bank0
RESET
0x00
PCI
-
RESET
SOFT
OFFSET
Table 47 − RTC and CMOS RAM Address Map
BASE
-
A
B
0
1
2
3
4
5
6
7
8
9
Table 46 − CMOS Run time Registers
-
VCC
POR
0x00
DATASHEET
BANK
RTC/CMOS Bank0
RTC/CMOS Bank0
CMOS Bank1
CMOS Bank1
REGISTER TYPE
-
POR
0x00
VTR
Page 98 of 259
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
Bit[0] = 1 : Lock CMOS RAM 0 – 1Fh
Bit[1] = 1 : Lock CMOS RAM 20 – 3Fh
Bit[2] = 1 : Lock CMOS RAM 40 – 5Fh
Bit[3] = 1 : Lock CMOS RAM 60 – 7Fh
Bit[7:4] Reserved, set to “0”
Once set, bit[3:0] can not be cleared by a write; bits[3:0]
are cleared on VCC Power On Reset, VCC Power Off, or
upon a PCI Reset. Once lock bits are set, the Host is
locked out of accessing the locked locations as long as
VCC is active. When VCC goes to 0V, the lock bits are
cleared.
Shadow of RTC/CMOS Bank 0 Index register
Bank 1:
D6
Register 0: Seconds
Register 1: Seconds Alarm
Register 2: Minutes
Register 3: Minutes Alarm
Register 4: Hours
Register 5: Hours Alarm
Register 6: Day of Week
Register 7: Day of Month
Register 8: Month
Register 9: Year
Register A:
Register B: (Bit 0 is Read
Only)
D5
FUNCTION
CMOS Address Register
CMOS Data Register
CMOS Address Register
CMOS Data Register
REGISTER FUNCTION
D4
DESCRIPTION
D3
Bit D7 of both CMOS Address
D2
D1
Rev. 04-30-07
D0