lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 205

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the
OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for 16 bit address
qualification.
Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be
relocated via the global configuration registers at 0x26 and 0x27.
SMSC LPC47S45x
LOGICAL
NUMBER
DEVICE
Config.
0x0A
0x0B
0x08
0x09
Port
Register Block
Config. Port
LOGICAL
Reserved
DEVICE
Runtime
SMBus
X-Bus
Table 84 − I/O Base Address Configuration Register Description
REGISTER
0x60, 0x61
0x26, 0x27
0x60,0x61
0x62,0x63
0x64,0x65
0x66,0x67
0x60,0x61
(Note 2)
INDEX
n/a
DATASHEET
ON 1 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 16 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 16 BYTE BOUNDARIES
on 128-byte boundaries
On 2-byte boundaries
on 8-byte boundaries
Mode 1 and Mode 2:
Mode 1 and Mode 2:
[0x0000:0x0FFF]
[0x0000:0x0FFC]
[0x0000:0x0FFC]
[0x0000:0x0FFC]
[0x0000:0x0FF0]
[0x0000:0x0FF0]
[0x0000:0x0F80]
[0x0100:0x0FF8]
Page 205 of 259
0x0100:0x0FFE
BASE I/O
(Note 1)
RANGE
Mode 1:
Mode 2:
Mode 1:
Mode 2:
n/a
+0: X-
+0: X-
+0: X-
+0: X-
n/a
+00 : PME_STS
.
.
.
(See Table in “Runtime Registers” section
for Full List)
+0: Control/Data
+1: Own Address
+2: Data
+3: Clock
See Configuration Registers in
Table 85. Accessed through the index
and DATA ports located at the
Configuration Port address and the
Configuration Port address +1
respectively.
BUS
BUS
BUS
BUS
CS0 A
CS1 A
CS2 A
CS3 A
BASE OFFSETS
DDRESS
DDRESS
DDRESS
DDRESS
FIXED
Rev. 08-10-09