lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 193

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

User Note 1: If this pin is used for Ring Indicator wakeup, either the RI2# event can be enabled via bit 1 in the
PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register.
User Note 2: In order to use the P12, P16 and P17 functions, the corresponding GPIO must be programmed for
output, non-invert, and push-pull output type.
The P12 function should not be selected on GP21 and GP 22 simultaneously. If P12 is selected on GP21 and GP22,
simultaneously, then P12 will function on GP22, not on GP21.
The P17 function should not be selected on GP20 and GP 62 simultaneously. If P17 is selected on GP20 and GP62,
simultaneously, then P17 will function on GP62, not on GP20.
Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME,
SMI and MSC status bits.
Note 2: These pins default to an output and LOW on VCC POR and PCI Reset.
Note 3: If the FDC function is selected on this pin (MTR1#, DS1#, DRVDEN0, DRVDEN1) then bit 6 of the FDD
Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control Register. Bit
7 of the FDD Mode Register will also affect the pin if the FDC function is selected.
Note 4: The IO_SMI# pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit
(EN_SMI, bit 7 of the SMI_EN2 register) is ‘0’. When the output buffer type is OD, IO_SMI# pin is floating when
inactive; when the output buffer type is push-pull, the IO_SMI# pin is high when inactive.
Note 5: If GP52 and GP53 are programmed for RXD2 and TXD2 functions and Serial Port 2 is programmed for IR
operation, then these pins will have IR functionality and when serial port 2 is disabled, the TXD2 pin will TRISTATE. If
these pins are programmed for IRRX and IRTX then these pins will have IR functionality and when serial port 2 is
disabled, the IRTX pin will go to its inactive state.
Note 6: The GP61 pin defaults to the LED function active (blinking at a 1 Hz rate, 50% duty cycle) on initial power up
(as long as the 32 kHz clock input is active).
Note 7: When Byte 1 (LSB) is read, by the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is
required the counter (Bytes 1 through 4) be read LSB to MSB. Latching of bytes for read output will not affect
continued counting
Note 8: In the present implementation of nPB_IN, pressing the button will always wake the machine (i.e., activate
nPS_ON).
Note 9: A soft reset only resets Bit[0] (LPC_REQ). Bit[1] will always reflect the current state of the arbitration logic.
SMSC LPC47S45x
Page 193 of 259
Rev. 08-10-09
DATASHEET