uja1078a NXP Semiconductors, uja1078a Datasheet
uja1078a
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uja1078a Summary of contents
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... Safe and controlled system start-up behavior • Detailed status reporting on system and sub-system levels The UJA1078A is designed to be used in combination with a microcontroller that incorporates a CAN controller. The SBC ensures that the microcontroller always starts controlled manner. Product data sheet ...
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... Wake-up via CAN, LIN or local wake-up pins with wake-up source detection 2 wake-up pins: UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... High-speed CAN/dual LIN core system basis chip voltages down to 4.5 V (e.g. during cranking), in accordance BAT voltages down to 5.5 V (e.g. during cranking) in accordance BAT All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1078ATW/5V0/WD HTSSOP32 UJA1078ATW/3V3/WD UJA1078ATW/5V0 UJA1078ATW/3V3 [1] UJA1078ATW/5V0xx versions contain regulator (V1); UJA1078ATW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF EN ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A 32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 LIN2 26 DLIN 25 LIN1 UJA1078A 24 SPLIT 23 GND 22 CANL 21 CANH WAKE2 18 WAKE1 17 LIMP 015aaa185 © NXP B.V. 2010. All rights reserved ...
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... IC and can be left floating, or can be connected to GND. 6. Functional description The UJA1078A combines the functionality of a high-speed CAN transceiver, two LIN transceivers, two voltage regulators and a watchdog (UJA1078A/xx/WD versions single, dedicated chip. It handles the power-up and power-down functionality of the ECU and ensures advanced system reliability ...
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... UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Figure 3. These modes are discussed in © NXP B.V. 2010. All rights reserved ...
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... V below BAT power-on threshold V th(det)pon CAN/LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1078A system controller UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip Overtemp V1: OFF V2: OFF limp home = LOW (active) CAN/LIN: Off and high resistance watchdog: OFF ...
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... Table low-power state (Lowpower mode; Section All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A ). In Off mode, the voltage regulators are disabled and Table 11). (Table 4). 6.1.3; the SBC will enter Standby mode) ...
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... STBCx = 1) with bus Section 6.7.1 Section 6.5.1 and Table Figure 4). All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A th(act)otp and Section 6.8.1). The watchdog is off and Section 6.5.1) system reset. The value of 11). © NXP B.V. 2010. All rights reserved. ...
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... Register map Write access bit read/write read only 0 = read/write read only 0 = read/write read only 0 = read/write read only All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A LSB 12 01 LSB Read/Write access bits 11... 0 WD_and_Status register ...
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... WAKE1 input voltage below switching threshold (V 1: WAKE1 input voltage above switching threshold (V wake-up 2 status 0: WAKE2 input voltage below switching threshold (V 1: WAKE2 input voltage above switching threshold (V All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A ) th(sw) ) th(sw) ) th(sw) ...
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... V1 threshold current for activating the external PNP transistor; load current rising mA; V1 threshold current for deactivating the external th(act)PNP PNP transistor; load current falling; I All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A = 50 mA; see Figure 7 th(deact)PNP = 15 mA; see Figure 7 th(deact)PNP © ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A . BAT . BAT © NXP B.V. 2010. All rights reserved ...
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... WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) WAKE2 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... CAN wake-up interrupt 0: no CAN wake-up interrupt pending 1: CAN wake-up interrupt pending All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... The on-chip oscillator is supplied by an internal supply that is connected to V and is independent of V1/V2. BAT 6.4 Watchdog (UJA1078A/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms. ...
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... SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor on RSTN pin) A watchdog overflow in Timeout mode requests a CI not already pending. The UJA1078A provides three signals for dealing with reset events: • RSTN pin input/output for performing a global ECU system reset or forcing an external reset • ...
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... ENC EN Behavior of EN pin Table set. If LHWC is already set when the system All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Section 6.6. the SBC leaving Off ) modes. A short reset pulse is th(rel)otp Table 11). 5) via the SPI interface. Pin EN will be HIGH when ...
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... Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional transceivers supplied by pin BAT and delivers up to 250 (depending on the UJA1078A version). To prevent the device overheating at high ambient temperatures or high average currents, an external PNP transistor can be connected as illustrated in configuration, the power dissipation is distributed between the SBC and the PNP transistor ...
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... V1 −165 mA 165 mA PNP current V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0) All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A 215 th(deact)PNP (PDC = 0) 015aaa111 015aaa075 © NXP B.V. 2010. All rights reserved. ...
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... V1. The alternative voltage source must be connected to pin V2. All internal functions (e.g. undervoltage protection) will work normally. 6.7 CAN transceiver The analog section of the UJA1078A CAN transceiver corresponds to that integrated into the TJA1042/TJA1043. The transceiver is designed for high-speed ( Mbit/s) CAN applications in the automotive industry, providing differential transmit and receive capability to a CAN protocol controller ...
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... CAN wake-up timing diagram All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Table 6) 6.6.3) Table 11). recessive t < t wake to(wake) ...
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... Pin TXDC has an internal pull-up towards V pin is left floating. 6.8 LIN1/LIN2 transceivers The analog sections of the UJA1078A LIN transceivers are identical to those integrated into the TJA1021. The transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN primarily intended for in-vehicle sub-networks using baud rates from 1 kBd kBd and is LIN 2 ...
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... LIN undervoltage recovery threshold, V BAT Table 6). The LIN transceivers can be woken up remotely via pins LIN1 wake(busdom)min All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Table Figure 1) - LIN recessive is (see Table 11). to guarantee safe, defined V1 © ...
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... WAKEx pin Wake-up int shows a typical circuit for implementing cyclic sampling of the wake-up inputs. All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A ), the transmitter is disabled, driving the bus Table 6). These bits can also be used to disable (Table 4) ...
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... WBIAS WAKE1 WAKE2 GND (Table 7). Clearing bits LWI1, LWI2 and CWI in Standby mode Section 6.1.6 “Overtemp All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A PDTA144E biasing of switches sample of sample of WAKEx WAKEx mode”). When the t ...
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... TEST2; referenced to pin BAT pin TEST2; referenced to other reference pins any other pin MM any pin CDM corner pins any other pin All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Min Max Unit −0 −0 0.3 ...
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... Product data sheet High-speed CAN/dual LIN core system basis chip Conditions . The rating for T limits the allowable combinations of power dissipation (P) and ambient vj vj All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Min Max Unit −40 °C [9] +150 −55 ° ...
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... Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm × will reduce thermal resistance (see All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A optional heatsink top layer optional heatsink top layer optional heatsink top layer ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A PCB Cu heatsink area (cm Conditions single-layer board four-layer board 015aaa138 Typ ...
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... CANH CANL 5.5 V < V < BAT contributed by WAKEx pin edge detectors; WIC1 = WIC2 = WAKE1 WAKE2 BAT All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; LIN2 (CANH-CANL unless BAT Min Typ 4 ...
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... LIN1 LIN2 LINx Active mode (dominant); STBCLx = TXDL1 TXDL2 mA; V DLIN LIN1 LIN2 All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ - - - - 100 - - - ...
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... VEXCTRL BAT load current increasing; external PNP transistor connected - see PDC 0 = 150 °C PDC PDC 1 = 150 °C PDC All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ 4 ...
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... SCSN 2. 5 0.4 V SCSN 2. 5 All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ Section 6.6 240 - 4 ...
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... for t < t WAKE BAT wake V = 0.4 V; LHC = 1 LIMP = −40 °C to 200 ° 1.4 V WBIAS All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ − −1500 - 4.9 - 200 ...
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... V CANH −30 V < V < +30 V CANL CAN Lowpower mode −12 V < V < +12 V CANH −12 V < V < +12 V CANL All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ 0. ...
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... TXDL1 TXDL2 LIN1 LIN2 BAT BAT GND LIN1 All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ 40 120 = − 5 ...
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... V; V TXDL1 TXDL2 LIN Active mode TXDL1 TXDL2 LIN Active mode 5 mA < I < DLIN All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ [ 0.6 × ...
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... TXDC RXDC Ω R (CANH-CANL 100 pF; C (CANH-CANL) RXDC f = 250 kHz TXDC All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; LIN2 (CANH-CANL unless BAT Min Typ 320 ...
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... BAT 7 LSC = 0 BAT V = 0.41V th(rec)RX(min) BAT V = 0.275V th(dom)RX(min) BAT 7.6 V; LSC = 0 BAT All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN2 (CANH-CANL) BAT Min Typ RXDC - ...
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... LIN timing diagram in bus(rec)(min) = 660 Ω kΩ 6.8 nF and illustrated in the LIN timing diagram in bus(rec)(max) All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Ω 500 ; R LIN1 LIN2 (CANH-CANL) Min Typ [1] 0.417 ...
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... GND t d(TXDC-busrec) t d(busdom-RXDC) t d(TXDCH-RXDCH) All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A after the start of the watchdog trig(wd)1 Table 4); valid in watchdog , but not more than t , after the start of the trig(wd)2 R CANH − R CANL C CANH − C CANL 015aaa079 0 ...
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... PD(RX)f PD(RX)r t PD(RX)r All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A BAT DLIN R LIN1 LIN1 SBC C LIN1 R LIN2 LIN2 C LIN2 GND 015aaa081 t bit V th(rec)RX(max) V th(dom)RX(max) ...
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... High-speed CAN/dual LIN core system basis chip T cy(clk clk(H) clk( su(D) h(D) MSB X MSB All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A t t SPILAG WH(S) LSB X t v(Q) floating LSB 015aaa045 © NXP B.V. 2010. All rights reserved ...
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... 0.30 0.20 11.1 5.1 6.2 3.6 0.19 0.09 10.9 4.9 6.0 3.4 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A detail 8.3 0.75 0.65 1 0.2 0.1 7.9 0.50 EUROPEAN PROJECTION SOT549 ...
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... Solder bath specifications, including temperature and impurities UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 21. All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A Figure 21) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 14. Revision history Table 14. Revision history Document ID Release date UJA1078A v.1 20100709 UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... High-speed CAN/dual LIN core system basis chip 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 July 2010 UJA1078A © NXP B.V. 2010. All rights reserved ...
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... Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 Introduction 6.2.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.3 WD_and_Status register 6.2.4 Mode_Control register . . . . . . . . . . . . . . . . . . 13 6.2.5 Int_Control register . . . . . . . . . . . . . . . . . . . . . 14 6.2.6 Int_Status register 6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 17 6.4 Watchdog (UJA1078A/xx/WD versions 6.4.1 Watchdog Window behavior . . . . . . . . . . . . . . 17 6.4.2 Watchdog Timeout behavior . . . . . . . . . . . . . . 18 6.4.3 Watchdog Off behavior . . . . . . . . . . . . . . . . . . 18 6.5 System reset 6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.3 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.1 Battery pin (BAT ...