uja1078a NXP Semiconductors, uja1078a Datasheet - Page 26

• Manufacturer Part Number: uja1078a
• Description: High-speed Can/dual Lin Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1078A
Product data sheet
6.9 Local wake-up input
triggered by a negative edge on the TXDL pin. If the pin remains LOW for longer than the
TXDL dominant time-out time (t
lines to a recessive state. The timer is reset by a positive edge on the TXDL pin.
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting
bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are
sampled continuously). The sampling will be performed on the rising edge of WBIAS (see
Figure
(WBC) in the Mode_Control register.
Figure 12
Fig 11. Wake-up pin sampling synchronized with WBIAS signal
11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit
Wake-up int
WAKEx pin
WBIAS pin
shows a typical circuit for implementing cyclic sampling of the wake-up inputs.
WBIASI
(internal)
All information provided in this document is subject to legal disclaimers.
enable bias
Rev. 01 — 9 July 2010
to(dom)TXDL
High-speed CAN/dual LIN core system basis chip
Table
), the transmitter is disabled, driving the bus
6). These bits can also be used to disable
disable bias
disable bias
wake level latched
(Table
UJA1078A
4).
© NXP B.V. 2010. All rights reserved.
015aaa078
26 of 53