at89c5131

Manufacturer Part Numberat89c5131
Description8-bit Flash Microcontroller With Full Speed Usb Device At89c5131
ManufacturerATMEL Corporation
at89c5131 datasheet
 
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Features
80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART)
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
32-Kbyte On-chip Flash In-System Programming through USB or UART
4-Kbyte EEPROM for Boot (3-Kbyte) and Data (1-Kbyte)
On-chip Expanded RAM (ERAM): 1024 Bytes
USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz DPLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to
6s at 4 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode)
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Low Power Voltage Range
– 3.0V to 3.6V
– 30 mA Max Operating Current (at 40 MHz)
– 100 µA Max Power-down Current
Industrial Temperature Range
Packages: PLCC52, VQFP64, MLF48, SO28
8-bit Flash
Microcontroller
with Full Speed
USB Device
AT89C5131
Rev. 4136C–USB–04/05

at89c5131 Summary of contents

  • Page 1

    ... Low Power Voltage Range – 3.0V to 3.6V – Max Operating Current (at 40 MHz) – 100 µA Max Power-down Current • Industrial Temperature Range • Packages: PLCC52, VQFP64, MLF48, SO28 8-bit Flash Microcontroller with Full Speed USB Device AT89C5131 Rev. 4136C–USB–04/05 ...

  • Page 2

    ... Kbyte), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator. In addition, AT89C5131 has an on-chip expanded RAM of 1024 bytes (ERAM), a dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA programmable LED current sources, a programmable hardware watchdog and a power-on reset ...

  • Page 3

    ... EUART 32Kx8 Flash 4Kx8 RAM + 256x8 BRG C51 CORE Parallel I/O Ports & Ext. Bus Timer 0 INT Timer 1 Ctrl Port 0Port 1 Port 2 Port 3 (2) (2) (2) (2) AT89C5131 (1) (1) (1) (1) (1) (1) (1) (1) ERAM 1Kx8 PCA SPI Timer2 TWI Key Watch Regu- USB Board Dog ...

  • Page 4

    ... Pinout Description Pinout AT89C5131 4 Figure 1. AT89C5131 52-pin PLCC Pinout P4.1/SDA 8 P2.3/A11 9 10 P2.4/A12 P2.5/A13 11 12 XTAL2 13 XTAL1 14 P2.6/A14 P2.7/A15 15 VDD 16 AVDD AVSS 19 P3.0/RxD P0.1/AD1 44 P0.2/AD2 43 RST 42 P0.3/AD3 41 VSS PLCC52 40 P0.4/AD4 39 P3.7/RD/LED3 38 P0 ...

  • Page 5

    ... Figure 2. AT89C5131 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 P2.7/A15 9 VDD 10 AVDD AVSS P3.0/RxD AT89C5131 P0.1/AD1 45 P0.2/AD2 44 RST 43 P0 ...

  • Page 6

    ... P4.1/SDA P2.3/A11 2 P2.4/A12 3 P2.5/A13 4 5 XTAL2 6 XTAL1 7 P2.6/A14 P2.7/A15 8 VDD 9 AVDD 10 11 AVSS 12 P3.0/RxD Figure 4. AT89C5131 28-pin SO Pinout P1.5/CEX2/KIN5/MISO 1 P1.6/CEX3/KIN6/SCK 2 P1.7/CEX4/KIN7/MOSI 3 P4.0/SCL 4 P4.1/SDA 5 XTAL2 6 XTAL1 7 8 VDD 9 AVSS 10 P3.0/RxD 11 PLLF VREF ...

  • Page 7

    ... Signals 4136C–USB–04/05 All the AT89C5131 signals are detailed by functionality on Table 1 through Table 12. Table 1. Keypad Interface Signal Description Signal Name Type Description Keypad Input Lines KIN[7:0) I Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt if enabled. Held line is reported in the KBCON register. ...

  • Page 8

    ... AT89C5131 8 Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued) Signal Name Type Description Timer Counter 0 External Clock Input T0 I When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer/Counter 1 External Clock Input T1 I When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count ...

  • Page 9

    ... Table 10. USB Signal Description Signal Name Type Description D+ I/O USB Data + signal D- I/O USB Data - signal USB Reference Voltage VREF O Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function. AT89C5131 Alternate Function AD[7: KIN[7:0] T2 T2EX ECI CEX[4:0] A[15:8] LED[3:0] RxD TxD INT0 ...

  • Page 10

    ... AT89C5131 10 Table 11. System Signal Description Signal Name Type Description Multiplexed Address/Data LSB for external access AD[7:0] I/O Data LSB for Slave port access (used for 8-bit and 16-bit modes) Address Bus MSB for external access A[15:8] I/O Data MSB for Slave port access (used for 16-bit mode only) Read Signal Read signal asserted during external data memory read operation ...

  • Page 11

    ... Table 12. Power Signal Description (Continued) Signal Name Type Description USB pull-up Controlled Output VREF is used to control the USB D+ 1.5 kΩ pull up. VREF O The Vref output is in high impedance when the bit DETACH is set in the USBCON register. AT89C5131 Alternate Function - 11 ...

  • Page 12

    ... SFR Mapping AT89C5131 12 The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

  • Page 13

    ... SSCON SSCS 0000 0000 1111 1000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT89C5131 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 UEPRST ...

  • Page 14

    ... AT89C5131 14 The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: Table 14. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register Program Status PSW D0h Word Stack Pointer SP 81h LSB of SPX Data Pointer Low byte DPL 82h ...

  • Page 15

    ... TF1 TR1 TF0 TR0 GATE1 C/T1# M11 M01 TF2 EXF2 RCLK TCLK FE/SM0 SM1 SM2 REN BRR AT89C5131 IE1 IT1 IE0 IT0 GATE0 C/T0# M10 M00 EXEN2 TR2 C/T2# CP/RL2# T2OE DCEN TB8 RB8 ...

  • Page 16

    ... Interrupt Priority Control High 0 IPL1 B2h Interrupt Priority Control Low 1 IPH1 B3h Interrupt Priority Control High 1 Table 21. PLL SFRs Mnemonic Add Name PLLCON A3h PLL Control PLLDIV A4h PLL Divider AT89C5131 CIDL WDTE ECOM0 CAPP0 ECOM1 CAPP1 ECOM2 CAPP2 ECOM3 CAPP3 ...

  • Page 17

    ... WUPCPU EORINT - - EWUPCPU EEORINT - - - - EPEN - - - DIR RXOUTB1 STALLRQ TXRDY - EP6RST EP5RST EP4RST - EP6INT EP5INT EP4INT - EP6INTE EP5INTE EP4INTE AT89C5131 KBF4 KBF3 KBF2 KBF1 KBE4 KBE3 KBE2 KBE1 KBLS4 KBLS3 KBLS2 KBLS1 STO SI AA CR1 SC1 SC0 - - SD4 ...

  • Page 18

    ... Auxiliary Register 0 AUXR1 A2h Auxiliary Register 1 CKCON0 8Fh Clock Control 0 CKCON1 AFh Clock Control 1 LEDCON F1h LED Control FCON D1h Flash Control EECON D2h EEPROM Contol AT89C5131 FDAT7 FDAT6 FDAT5 FDAT4 BYCT7 BYCT6 BYCT5 BYCT4 - - - - FNUM7 FNUM6 FNUM5 ...

  • Page 19

    ... Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are gen- erated by this controller. The AT89C5131 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5) that can be configured with off-chip components as a Pierce oscillator (see Figure 6). Value of capacitors and crystal characteristics are detailed in the section “ ...

  • Page 20

    ... AT89C5131 20 Figure 6. Crystal Connection VSS The AT89C5131 PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 7 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block ...

  • Page 21

    ... The typical divider values are shown in Table 27. Table 27. Typical Divider Values Oscillator Frequency 3 MHz 6 MHz 8 MHz 12 MHz 16 MHz 18 MHz 20 MHz 24 MHz 32 MHz 40 MHz AT89C5131 PLL Programming Configure Dividers N3:0 = xxxxb R3:0 = xxxxb Enable PLL PLLEN = 1 PLL Locked? LOCK = 1? R+1 N+1 16 ...

  • Page 22

    ... Registers AT89C5131 22 Table 28. CKCON0 (S:8Fh) Clock Control Register WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Watchdog Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, ...

  • Page 23

    ... Clear by hardware when PLL is unlocked. Reset Value = 0000 0000b Table 31. PLLDIV (S:A4h) PLL Divider Register Bit Bit Number Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits Reset Value = 0000 0000 AT89C5131 EXT48 PLLEN ...

  • Page 24

    ... Figure 10. Use of Dual Pointer 7 0 DPS AUXR1(A2H) AT89C5131 24 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1 ...

  • Page 25

    ... DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C5131 25 ...

  • Page 26

    ... Access Memory Interface AT89C5131 26 The AT89C5131 implement 16/32 Kbytes of on-chip program/code memory. Figure 11 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V age ...

  • Page 27

    ... This signal is active low during external code fetch or external code read (MOVC instruction). This section describes the bus cycles the AT89C5131 executes to fetch code (see Figure 13) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode ...

  • Page 28

    ... FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Space Column Latches AT89C5131 28 AT89C5131 features two on-chip Flash memories: • Flash memory FM0: containing 16/32 Kbytes of program memory (user space) organized into 128-byte pages, • Flash memory FM1: 3 Kbytes for bootloader and Application Programming Interfaces (API). ...

  • Page 29

    ... User Extra Row Security Space Reserved A X AT89C5131 FM0 Adressable Space User (0000h-FFFFh) Extra Row(FF80h-FFFFh) Hardware Security (0000h) reserved FMOD1 FMOD0 Operation action Write the column latches in user 0 0 space action Write the column latches in extra row ...

  • Page 30

    ... Status of the Flash Memory Selecting FM0/FM1 AT89C5131 30 The Flash memory enters a busy state as soon as programming is launched. In this state, the memory is not available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming ...

  • Page 31

    ... The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. AT89C5131 Column Latches Loading Column Latches Mapping FPS = 1 Data Load ...

  • Page 32

    ... Extra Row AT89C5131 32 The following procedure is used to program the Extra Row space and is summarized in Figure 16: • Load data in the column latches from address FF80h to FFFFh. • Disable the interrupts. • Launch the programming by writing the data sequence 52h followed by A2h in FCON register. ...

  • Page 33

    ... Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared. • Enable the interrupts. Figure 17. Hardware Programming Procedure AT89C5131 Flash Spaces Programming FCON = 0Ch Data Load DPTR = 00h ACC = Data ...

  • Page 34

    ... Reading the Flash Spaces User Extra Row Hardware Security AT89C5131 34 The following procedure is used to read the User space and is summarized in Figure 18: • Map the User space by writing 00h in FCON register. • Read one byte in Accumulator by executing MOVC A, @A+DPTR with & ...

  • Page 35

    ... Clear to re-map the data memory space. Flash Mode 2-1 FMOD1:0 See Table 34 or Table 35. Flash Busy Set by hardware when programming is in progress. 0 FBUSY Clear by hardware when programming is done. Can not be cleared by software. Reset Value = 0000 0000b AT89C5131 FPL0 FPS FMOD1 FMOD0 1 0 FBUSY 35 ...

  • Page 36

    ... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C5131. The bootloader and the Application Programming Interface (API) routines are located in the Boot ROM ...

  • Page 37

    ... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called “Extra Flash Memory”, is not in the internal Flash program memory addressing space. The only hardware registers of the AT89C5131 is called Hardware Security Byte (HSB). Table 37. Hardware Security Byte (HSB ...

  • Page 38

    ... Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers are described in Table 39. AT89C5131 LB2 Protection Description U No program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching code ...

  • Page 39

    ... Default value FCh – 1011 1000b – 0FFh – FFh – 58h Atmel C51 X2, Electrically D7h Erasable F7h AT89C5131 32 Kbyte FBh AT89C5131 16 Kbyte AT89C5131 32 Kbyte, EFh revision 0 AT89C5131 16 Kbyte, FFh revision LB1 and Table 41. 0 LB0 4136C–USB–04/05 ...

  • Page 40

    ... X: don’t care 4. WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C5131 parts are delivered with the ISP boot in the Flash memory. After ISP or par- allel programming, the possible contents of the Flash memory are summarized in Figure 19: ...

  • Page 41

    ... Description Write Data in the Column Latches Programming Read Data AT89C5131 40 The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming) ...

  • Page 42

    ... EEE latches) Clear to map the ERAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. 0 EEBUSY Cleared by hardware when programming is done. Cannot be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable AT89C5131 EEPL0 - - 1 0 EEE EEBUSY ...

  • Page 43

    ... With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C5131 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • ...

  • Page 44

    ... These Bytes are reserved for customer use read or modify these Bytes, the APIs are used. RESET BLJB == 0 ? ENBOOT = F400h Bootloader in FM1 AT89C5131 bit ENBOOT in AUXR1 Register Is Initialized with BLJB Inverted. Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset. 43 ...

  • Page 45

    ... During the first programming, the user can define a configuration on Port1 that will be recognized by the chip as the hardware conditions during a Reset. If this condition is met, the chip will start executing the bootloader at the end of the Reset. See a detailed description in the applicable Document. – Datasheet Bootloader USB AT89C5131. Default Value Address 58h 30h ...

  • Page 46

    ... The value read from this bit is indeterminate. 2-0 LB2:0 Lock Bits Default value after erasing chip: FFh Notes: 1. Only the 4 MSB bits can be access by software. 2. The 4 LSB bits can only be access by parallel mode. AT89C5131 OSCON0 - LB2 1 oscillator is configured to run from MHz ...

  • Page 47

    ... Part Number ERAM Size AT89C5131 1024 The AT89C5131 has on-chip data memory that is mapped into the following four sepa- rate segments. 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only ...

  • Page 48

    ... The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM. The M0 bit allows to stretch the ERAM timings set, the read and write pulses are extended from clock periods. This is useful to access external slow peripherals. AT89C5131 47 ...

  • Page 49

    ... AT89C5131 48 Table 46. AUXR Register AUXR - Auxiliary Register (8Eh DPU - M0 Bit Bit Number Mnemonic Description Disable Weak Pull Up 7 DPU Cleared to enabled weak pull up on standard Ports. Set to disable weak pull up on standard Ports. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit ...

  • Page 50

    ... Timer 2 Auto-reload Mode 4136C–USB–04/05 The Timer 2 in the AT89C5131 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2 controlled by T2CON (Table 47) and T2MOD (Table 48) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F (counter operation) as the timer clock input ...

  • Page 51

    ... Figure 23. Auto-reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH Programmable Clock Output AT89C5131 C/T2 T2CON (DOWN COUNTING RELOAD VALUE) FFh (8-bit) (8-bit) TL2 (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock gen- erator (See Figure 24) ...

  • Page 52

    ... It is possible to use Timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 24. Clock-out Mode C/ CLK PERIPH T2 T2EX AT89C5131 TR2 T2CON TH2 TL2 (8-bit) (8-bit) RCAP2H RCAP2L ...

  • Page 53

    ... AT89C5131 52 Table 47. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1 ...

  • Page 54

    ... Timer 2 Output Enable bit 1 T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable AT89C5131 T2OE 0 DCEN 53 ...

  • Page 55

    ... Programmable Counter Array (PCA) AT89C5131 54 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...

  • Page 56

    ... CPS0 PCA Enable Counter Overflow Interrupt 0 ECF Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. Reset Value = 00XX X000b Not bit addressable AT89C5131 To PCA modules overflow Bit Up/Down Counter CMOD ECF 0xD9 CCON 0xD8 ...

  • Page 57

    ... AT89C5131 56 The CMOD register includes three additional bits associated with the PCA (See Figure 25 and Table 49). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog function on module 4. • The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR set when the PCA timer overflows ...

  • Page 58

    ... PCA counter and the module's capture/compare register. • The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and AT89C5131 CCON 0xD8 To Interrupt priority decoder IE ...

  • Page 59

    ... AT89C5131 58 the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 52 shows the CCAPMn settings for the various PCA functions. ...

  • Page 60

    ... CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (see Table 53 and Table 54) AT89C5131 PWM ECCF MATn ...

  • Page 61

    ... AT89C5131 60 Table 53. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh) ...

  • Page 62

    ... CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 28). AT89C5131 ...

  • Page 63

    ... Figure 28. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode AT89C5131 62 CCF4 CF CR CCAPnH CCAPnL Match 16-bit Comparator CH CL PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE Note: 1. Only for Module 4 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen ...

  • Page 64

    ... CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C5131 CCON 0xD8 PCA IT ...

  • Page 65

    ... PCA Watchdog Timer AT89C5131 64 Figure 30. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge ...

  • Page 66

    ... Serial I/O Port Framing Error Detection 4136C–USB–04/05 The serial I/O port in the AT89C5131 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simul- taneously and at different baud rates ...

  • Page 67

    ... Automatic Address Recognition Given Address AT89C5131 66 Figure 33. UART Timings in Modes 2 and 3 RXD D0 D1 Start Bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...

  • Page 68

    ... XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable AT89C5131 ...

  • Page 69

    ... Baud Rate Selection for UART for Mode 1 and 3 Baud Rate Selection Table for UART Internal Baud Rate Generator (BRG) AT89C5131 68 SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers ...

  • Page 70

    ... CLK PERIPH BRR 4136C–USB–04/05 auto reload counter 0 /6 BRG 1 BRL SPD • The baud rate for UART is token by formula: Baud_Rate = (BRL) = 256 - AT89C5131 /2 overflow 0 INT_BRG 1 SMOD1 SMOD1 CLK PERIPH (1-SPD [256 - (BRL)] SMOD1 ...

  • Page 71

    ... AT89C5131 70 Table 57. SCON Register – SCON Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. ...

  • Page 72

    ... SADDR - Slave Address Register for UART (A9h – – – Reset Value = 0000 0000b SBUF - Serial Buffer Register for UART (99h – – – Reset Value = XXXX XXXXb AT89C5131 MHz OSCA Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0.63 178 ...

  • Page 73

    ... AT89C5131 72 BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah – – – Reset Value = 0000 0000b Table 58. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag ...

  • Page 74

    ... Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C5131 POF GF1 GF0 rises from 0 to its nominal voltage ...

  • Page 75

    ... AT89C5131 74 Table 60. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved 6 - The value read from this bit is indeterminate. Do not set this bit Reserved ...

  • Page 76

    ... Individual Enable 4136C–USB–04/05 The AT89C5131 has a total of 15 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 36 ...

  • Page 77

    ... Registers AT89C5131 76 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register (Table 62). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority lev- els by setting or clearing a bit in the Interrupt Priority register (Table 63 ...

  • Page 78

    ... Timer 0 overflow interrupt Enable bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C5131 ET1 EX1 ET0 1 0 EX0 77 ...

  • Page 79

    ... AT89C5131 78 Table 63. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit 6 PPCL Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...

  • Page 80

    ... External interrupt 0 Priority High bit PX0H PX0L PX0H Reset Value = X000 0000b Not bit addressable AT89C5131 PSH PT1H PX1H PT0H Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest Highest Priority Level Lowest ...

  • Page 81

    ... AT89C5131 80 Table 65. IEN1 Register IEN1 - Interrupt Enable Register (B1h EUSB - Bit Bit Number Mnemonic Description 7 - Reserved USB Interrupt Enable bit 6 EUSB Cleared to disable USB interrupt. Set to enable USB interrupt Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable bit 2 ESPI Cleared to disable SPI interrupt. ...

  • Page 82

    ... SPI Interrupt Priority bit 2 PSPIL Refer to PSPIH for priority level. TWI Interrupt Priority bit 1 PTWIL Refer to PTWIH for priority level. Keyboard Interrupt Priority bit 0 PKBL Refer to PKBH for priority level. Reset Value = X0XX X000b Not bit addressable AT89C5131 PSPIL PTWIL 0 PKBDL 81 ...

  • Page 83

    ... AT89C5131 82 Table 67. IPH1 Register IPH1 - Interrupt Priority High Register (B3h PUSBH - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit PUSBH PUSBL Priority Level PUSBH ...

  • Page 84

    ... UART 6 7 Timer PCA 8 8 Keyboard USB 15 15 AT89C5131 Interrupt Request IE0 TF0 IE1 IF1 RI+TI TF2+EXF2 CF + CCFn (n = 0-4) KBDIT TWI TWIIT SPI SPIIT UEPINT + USBINT Vector Address 0000h 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h ...

  • Page 85

    ... Interrupt AT89C5131 84 The AT89C5131 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes. ...

  • Page 86

    ... Keyboard interrupt request if the KBIE.1 bit in KBIE register is set. Must be cleared by software. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Must be cleared by software. Reset Value = 0000 0000b AT89C5131 KBF4 KBF3 KBF2 KBF1 1 ...

  • Page 87

    ... AT89C5131 86 Table 70. KBE Register KBE - Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit ...

  • Page 88

    ... Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b AT89C5131 KBLS4 KBLS3 KBLS2 KBLS1 ...

  • Page 89

    ... Programmable LED AT89C5131 88 AT89C5131 have programmable LED current sources, configured by the regis- ter LEDCON. Table 72. LEDCON Register LEDCON (S:F1h) LED Control Register LED3 LED2 Bit Bit Number Mnemonic Description Port/LED3 Configuration 0 0 7:6 LED3 Port/LED2 Configuration 0 0 5:4 LED2 ...

  • Page 90

    ... Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port AT89C5131 Slave 1 Slave 3 ...

  • Page 91

    ... Baud Rate AT89C5131 90 pins (Figure 39). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Section “ ...

  • Page 92

    ... When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 41). AT89C5131 Internal Bus SPDAT Shift Register ...

  • Page 93

    ... Master Mode Slave Mode Transmission Formats AT89C5131 92 Figure 41. Full-duplex Master/Slave Interconnection 8-bit Shift Register SPI Clock Generator Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one Master SPI device can initiate transmissions. Software begins the trans- mission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT) ...

  • Page 94

    ... MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 39). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. AT89C5131 ...

  • Page 95

    ... Mode Fault (MODF) Write Collision (WCOL) Overrun Condition Interrupts AT89C5131 94 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control ...

  • Page 96

    ... Set to have the SCK set to “1” in idle state. Clock Phase Cleared to have the data sampled when the SCK leaves the idle state (see 3 CPHA CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). AT89C5131 SPI CPU Interrupt Request SPI Receiver/Error CPU Interrupt Request 4 3 ...

  • Page 97

    ... Serial Peripheral Status Register (SPSTA) AT89C5131 96 Bit Number Bit Mnemonic Description SPR2 SPR1 2 SPR1 SPR0 Reset Value = 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to signal the following conditions: • ...

  • Page 98

    ... Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow AT89C5131 ...

  • Page 99

    ... Two Wire Interface ( TWI Introduction AT89C5131 98 ) The Synchronous Serial Link Controller (SSLC) provides the selection of one synchro- nous serial interface among the two most popular ones: • Two Wire Interface (TWI). • Serial Peripheral Interface (SPI) When an interface is selected, the other is no longer available, its usage is exclusive. ...

  • Page 100

    ... Stage 4136C–USB–04/05 SSADR Address Register Comparator SSDAT Shift Register Arbitration and Sink Logic Timing and Control Logic Serial clock generator Timer 1 overflow SSCON Control Register Status Status Decoder Bits SSCS Status Register AT89C5131 8 ACK 8 F CLK PERIPH/ 4 Interrupt ...

  • Page 101

    ... SDA SCL S start condition AT89C5131 100 The CPU interfaces to the TWI logic via the following four 8-bit special function regis- ters: the Synchronous Serial Control register (SSCON; Table 85 and Table 79), the Synchronous Serial Data register (SSDAT; Table 86), the Synchronous Serial Control and Status register (SSCS ...

  • Page 102

    ... SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted. AT89C5131 ...

  • Page 103

    ... Slave Receiver Mode Slave Transmitter Mode AT89C5131 102 SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table . After a repeated START condition (state 10h) SSLC may switch to the master transmitter mode by loading SSDAT with SLA+W. In the slave receiver mode, a number of data bytes are received from a master transmit- ter (Figure 51) ...

  • Page 104

    ... SDA and SLC must be set to logic 1. CR2 CR1 CR0 AT89C5131 Bit Frequency (kHz MHz MHz OSCA OSCA 47 62.5 53.5 71.5 62 100 12.5 16.5 100 - - - 0.5 < . < 62.5 0.67 < . < 83 (reload value range: F divided by OSCA ...

  • Page 105

    ... Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master AT89C5131 104 Data 18h A P 20h Other master ...

  • Page 106

    ... AT89C5131 Next Action Taken by Two-wire Hardware X SLA+W will be transmitted. SLA+W will be transmitted. X SLA+R will be transmitted. X Logic will switch to master receiver mode Data byte will be transmitted. X Repeated START will be transmitted. X STOP condition will be transmitted and SSSTO flag X will be reset ...

  • Page 107

    ... Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or acknowledge bit Arbitration lost and addressed as slave From master to slave From slave to master AT89C5131 106 MR Data 50h 40h A P 48h Other master ...

  • Page 108

    ... AT89C5131 Next Action Taken by Two-wire Hardware X SLA+R will be transmitted. SLA+R will be transmitted. X SLA+W will be transmitted. X Logic will switch to master transmitter mode. Two-wire bus will be released and not addressed X slave mode will be entered. A START condition will be transmitted when the bus X becomes free ...

  • Page 109

    ... Reception of the general call address and one or more data bytes. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT89C5131 108 S SLA W A 60h A 68h General Call ...

  • Page 110

    ... Read data byte or Read data byte AT89C5131 AA Next Action Taken By 2-wire Software Data byte will be received and NOT ACK will be 0 returned Data byte will be received and ACK will be 1 returned Data byte will be received and NOT ACK will be ...

  • Page 111

    ... Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START condition has been A0h received while still addressed as slave AT89C5131 110 Application Software Response To/from SSDAT To SSCON STA STO SI Read data byte or 0 ...

  • Page 112

    ... Load data byte X 0 Load data byte Load data byte X 0 Load data byte Load data byte X 0 AT89C5131 Data A B8h C0h All 1’s A C8h SI AA Next Action Taken By 2-wire Software Last data byte will be transmitted and NOT ACK 0 ...

  • Page 113

    ... Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been transmitted (AA=0); ACK has been received AT89C5131 112 Application Software Response To/from SSDAT To SSCON STA STO No SSDAT action SSDAT action or ...

  • Page 114

    ... Address bit 6 or Data bit 6. 5 SD5 Address bit 5 or Data bit 5. 4 SD4 Address bit 4 or Data bit 4. 3 SD3 Address bit 3 or Data bit 3. 2 SD2 Address bit 2 or Data bit 2. AT89C5131 STO SI AA CR1 SD4 SD3 SD2 SD1 4 ...

  • Page 115

    ... AT89C5131 114 Bit Bit Number Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 87. SSCS (094h) Read - Synchronous Serial Control and Status Register SC4 SC3 SC2 Bit Bit Number Mnemonic Description 0 0 Always zero ...

  • Page 116

    ... USB Mass Storage Class Bulk- only Transport AT89C5131 114 The AT89C5131 implements a USB device controller supporting full speed data transfer in accordance with the USB 1.1 and 2.0 Specifications. In addition to the default control endpoint 0, it provides 6 other endpoints, which can be configured in control, bulk, inter- rupt or isochronous modes: • ...

  • Page 117

    ... DFU functions. The Run-Time configuration co- exists with the usual functions of the device, which may be USB Mass Storage for the AT89C5131 used to initiate DFU from the normal operating mode. The DFU config- uration is used to perform the firmware update after device re-configuration and USB reset ...

  • Page 118

    ... Serial Interface Engine (SIE) Figure 54. SIE Block Diagram End of Packet Detection Start of Packet Detection D+ D- Clk48 (48 MHz) AT89C5131 116 The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and un-stuffing. • CRC generation and checking. • ...

  • Page 119

    ... C51 Endpoint FIFO write 4136C–USB–04/05 The Function Interface Unit provides the interface between the AT89C5131 and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Asynchronous Information ...

  • Page 120

    ... UEPSTA0 Endpoint 0 UBYCTH0 UEPSTA6 Endpoint 6 UBYCTH6 AT89C5131 118 • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” on page 19). The USB controller will be then enabled by setting the EUSB bit in the USBCON register. • ...

  • Page 121

    ... Summary of Endpoint Configuration: Do not forget to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers. Table 88. Summary of Endpoint Configuration Endpoint Configuration Disabled Control Bulk-in Bulk-out Interrupt-In Interrupt-Out Isochronous-In Isochronous-Out AT89C5131 EPEN EPDIR EPTYPE 0b Xb XXb 1b Xb 00b 1b 1b 10b ...

  • Page 122

    ... UEPSTA0 Endpoint 0 UBYCTH0 UEPSTA6 Endpoint 6 UBYCTH6 AT89C5131 120 • Endpoint FIFO reset Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers), and resets the data toggle bit (DTGL bit in UEPCONX). ...

  • Page 123

    ... If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host. AT89C5131 UFI C51 ...

  • Page 124

    ... Bulk/Interrupt OUT Transactions in Ping-pong Mode AT89C5131 122 Figure 60. Bulk/Interrupt OUT Transactions in Ping-pong Mode HOST OUT DATA0 (n Bytes) ACK DATA1 (m Bytes) OUT ACK OUT DATA0 (p Bytes) ACK An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller ...

  • Page 125

    ... The firmware will clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware will never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller. AT89C5131 C51 Endpoint FIFO Write Byte 1 Endpoint FIFO Write Byte 2 ...

  • Page 126

    ... Bulk/Interrupt IN Transactions in Ping-pong Mode AT89C5131 124 Figure 62. Bulk/Interrupt IN Transactions in Ping-pong Mode HOST UFI IN NACK IN DATA0 (n Bytes) ACK TXCMPL IN DATA1 (m Bytes) ACK TXCMPL IN DATA0 (p Bytes) ACK An endpoint will be first enabled and configured before being able to send Bulk or Inter- rupt packets. The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint ...

  • Page 127

    ... IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page 123). To send a STALL handshake, see “STALL Handshake” on page 128. • For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 121). AT89C5131 125 ...

  • Page 128

    ... Transactions in Standard Mode Isochronous OUT Transactions in Ping-pong Mode AT89C5131 126 An endpoint will be first enabled and configured before being able to receive Isochro- nous packets. When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corre- sponding endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers ...

  • Page 129

    ... The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won’t send anything at each IN requests concerning this bank. The firmware will never write more bytes than supported by the endpoint FIFO. AT89C5131 127 ...

  • Page 130

    ... STALL Handshake Start of Frame Detection Frame Number Data Toggle Bit AT89C5131 128 The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con- troller is still enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit to allow the next USB reset detection ...

  • Page 131

    ... The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. Figure 63. Example of a Suspend/Resume Management Detection of a SUSPEND State Detection of a RESUME State AT89C5131 USB Controller Init SPINT Clear SPINT Set SUSPCLK Disable PLL ...

  • Page 132

    ... Upstream Resume Figure 64. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND State Upstream RESUME Sent AT89C5131 130 A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up purpose DEVICE_REMOTE_WAKEUP, the firmware will set to 1 the RMWUPE bit in the USB- CON register to enable this functionality ...

  • Page 133

    ... D+ USB Controller D- 4136C–USB–04/05 In order to be re-enumerated by the Host, the AT89C5131 has the possibility to simulate a DETACH - ATTACH of the USB bus. The V output voltage is between 3.0V and 3.6V. This output can be connected to the REF D+ pull-up as shown in Figure 65. This output can be put in high-impedance when the DETACH bit is set the USBCON register. Maintaining this output in high imped- ance for more than 3 µ ...

  • Page 134

    ... USB Interrupt Control System AT89C5131 132 Table 89. Priority Levels IPHUSB IPLUSB shown in Figure 68, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see Table 96 on page 139). This bit is set by hardware when the Host accept a In packet. • ...

  • Page 135

    ... Figure 68. USB Interrupt Control Block Diagram Endpoint 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 4136C–USB–04/05 EPXINT UEPINT.X EPXIE UEPIEN.X AT89C5131 EUSB IE1.6 133 ...

  • Page 136

    ... USB Registers AT89C5131 134 Table 90. USBCON Register USBCON (S:BCh) USB Global Control Register USBE SUSPCLK SDRMWUP Bit Number Bit Mnemonic Description USB Enable Set this bit to enable the USB controller. 7 USBE Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controller clock inputs ...

  • Page 137

    ... This bit is set by hardware when a USB Suspend (Idle bus for three frame periods state for 3 ms) is detected. This triggers a USB interrupt when 0 SPINT ESPINT is set in see Figure 92 on page 136. This bit will be cleared by software BEFORE any other USB operation to re- activate the macro. Reset Value = 00h AT89C5131 EORINT SOFINT - 1 ...

  • Page 138

    ... AT89C5131 136 Table 92. USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU Bit Number Bit Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. Enable Wake Up CPU Interrupt Set this bit to enable Wake Up CPU Interrupt. (See “USBIEN Register ...

  • Page 139

    ... USB Endpoint Number), UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) or UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register. This value can Reset Value = 00h AT89C5131 ...

  • Page 140

    ... AT89C5131 138 Table 95. UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register EPEN - - Bit Bit Number Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. 7 EPEN Endpoint 0 will always be enabled after a hardware or USB bus reset and participate in the device configuration ...

  • Page 141

    ... Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 143). This bit will be cleared by the device firmware before setting TXRDY. Reset Value = 00h 4136C–USB–04/ STALLRQ TXRDY STL/CRC AT89C5131 RXSETUP RXOUTB0 0 TXCMP 139 ...

  • Page 142

    ... AT89C5131 140 Table 97. UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint EPNUM set in UEPNUM Register UEPNUM (S:C7h FDAT7 FDAT6 FDAT5 Bit Bit Number Mnemonic Description Endpoint X FIFO data FDAT [7:0] Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM) ...

  • Page 143

    ... Most Significant Byte of the byte count of a received data packet. The Least 2-0 BYCT[10:8] significant part is provided by UBYCTLX Register UBYCTLX (S:E2h) USB Byte Count Low Register EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) (see Figure 98 on page 140). (S:C7h) USB Endpoint Number) Reset Value = 00h AT89C5131 ...

  • Page 144

    ... AT89C5131 142 Table 100. UEPRST Register UEPRST (S:D5h) USB Endpoint FIFO Reset Register EP6RST EP5RST Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon ...

  • Page 145

    ... The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, 0 EP0INT RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared Reset Value = 00h AT89C5131 EP4INT EP3INT EP2INT ...

  • Page 146

    ... AT89C5131 144 Table 102. UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register EP6INTE EP5INTE Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Endpoint 6 Interrupt Enable 6 EP6INTE Set this bit to enable the interrupts for this endpoint. ...

  • Page 147

    ... Bit Bit Number Mnemonic Description Frame Number FNUM[7:0] are the lower 8 bits of the 11-bit Frame Number (See “UFNUMH FNUM[7:0] Register UFNUMH (S:BBh, read-only) USB Frame Number High Register” on page 145). Reset Value = 00h AT89C5131 CRCERR - FNUM10 FNUM4 ...

  • Page 148

    ... In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT89C5131 into power-down mode. can be lowered to save further CC ...

  • Page 149

    ... Mode Memory ALE PSEN Idle Internal 1 Idle External 1 Power-down Internal 0 Power-down External 0 Note: 1. Port 0 can force a 0 level. A “one” will leave port floating. AT89C5131 Active Phase PORT0 PORT1 PORT2 Port Port 1 Port Data (1) Data Data Port 1 Floating Address Data Port ...

  • Page 150

    ... Registers AT89C5131 148 Table 106. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial Port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial Port Mode bit 0 6 SMOD0 Set to select FE bit in SCON register. ...

  • Page 151

    ... WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C5131 , where T CLK PERIPH 7 counter has been added to extend the Time-out = 12 MHz. To manage this feature, refer to OSCA ...

  • Page 152

    ... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C5131 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...

  • Page 153

    ... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C5131 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 109 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...

  • Page 154

    ... Reduced EMI Mode AT89C5131 152 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...

  • Page 155

    ... Freq (MHz CCOP I = 0.6 Freq (MHz CCIDLE AT89C5131 Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...

  • Page 156

    ... OL Port Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. AT89C5131 154 Min 2 0.15 PFDM . I would be slightly higher if a crystal oscillator used (see Figure CC CC ...

  • Page 157

    ... RST EA (NC) XTAL2 XTAL1 V SS Figure 73. Clock Signal Waveform for I V -0.5V CC 0.45V T CHCL Min ± 20 AT89C5131 All other pins are disconnected All other pins are disconnected. Tests in Active and Idle Modes CC 0.7V CC 0.2V -0 CLCH ...

  • Page 158

    ... USB DC Parameters AT89C5131 156 BUS GND 3 2 USB “B” Receptacle 1.5 kΩ 27Ω pad Symbol Parameter V USB Reference Voltage REF V Input High Voltage for D+ and D- (Driven Input High Voltage for D+ and D- (Floating) IHZ V Input Low Voltage for D+ and D- ...

  • Page 159

    ... ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In PLIV T Input Instruction Hold after PSEN PXIX T Input Instruction Float after PSEN PXIZ T Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ AT89C5131 = 3.3V ±10 MHz. = 3.3V ± 10%. 157 ...

  • Page 160

    ... AT89C5131 158 Table 113. AC Parameters for a Fix Clock ( MHz) Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Table 114. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL ...

  • Page 161

    ... AVDV T ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C5131 T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 159 ...

  • Page 162

    ... AT89C5131 160 Table 116. AC Parameters for a Variable Clock ( MHz) Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Min Max 130 130 100 0 30 160 165 50 100 75 10 160 Units ...

  • Page 163

    ... Min QVWH T Min WHQX T Max RLAZ T Min WHLH T Max WHLH T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT89C5131 Standard Clock X2 Clock X Parameter 2 4 ...

  • Page 164

    ... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C5131 162 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Table 118. Symbol Description ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 119 ...

  • Page 165

    ... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ±20 mA. occurs AT89C5131 SET TI VALID VALID VALID ...

  • Page 166

    ... This propagation delay is dependent on variables such as temperature and pin loading. Propa- gation also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C5131 164 Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE5 ...

  • Page 167

    ... Input PSEN Valid to RST Edge SVRL T Input PSEN Hold after RST Edge RLSX T Flash Internal Busy (Programming) Time BHBL Figure 74. Flash Memory - ISP Waveforms RST PSEN1 Figure 75. Flash Memory - Internal Busy Waveforms FBUSY bit AT89C5131 Conditions L Low V Valid X No Longer Valid Min Typ ...

  • Page 168

    ... USB AC Parameters V CRS Differential Data Lines AT89C5131 166 Rise Time 90% 90% 10 Table 124. USB AC Parameters Symbol Parameter t Rise Time R t Fall Time F t Full-speed Data Rate FDRATE V Crossover Voltage CRS Source Jitter Total to Next t DJ1 Transaction Source Jitter Total for Paired ...

  • Page 169

    ... Pack -Die form 4136C–USB–04/05 (Kbytes) Supply Voltage 16 2.7 to 5.5V 16 2.7 to 5.5V 16 2.7 to 5.5V 32 2.7 to 5.5V 32 2.7 to 5.5V 32 2.7 to 5.5V 32 2.7 to 5.5V AT89C5131 Temperature Range Package Industrial Green VQFP64 Industrial Green QFN32 Industrial Green PLCC52 Industrial VQFP64 Industrial QFN32 Industrial PLCC52 Industrial Green VQFP64 Packing (1) Tray ...

  • Page 170

    ... Packaging Information 64-lead VQFP AT89C5131 168 4136C–USB–04/05 ...

  • Page 171

    ... PLCC 4136C–USB–04/05 AT89C5131 169 ...

  • Page 172

    ... QFN Datasheet Change Log Changes from 4337A - 10/04 to 4337B - 12/04 AT89C5131 170 1. Added 16 Kbytes version of Product. 4136C–USB–04/05 ...

  • Page 173

    Table of Contents 4136C–USB–04/05 Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 3 Pinout Description ................................................................................ 4 Pinout.................................................................................................................... 4 Signals ...................................................................................................................7 SFR Mapping ....................................................................................... 12 Clock Controller .................................................................................. 19 Introduction ......................................................................................................... 19 Oscillator............................................................................................................. 19 PLL ..................................................................................................................... 20 Registers..............................................................................................................22 Dual ...

  • Page 174

    Application-Programming-Interface .................................................................... 44 XROW Bytes....................................................................................................... 44 Hardware Conditions .......................................................................................... 44 Hardware Security Byte ...................................................................................... 45 On-chip Expanded RAM (ERAM) ....................................................... 46 Timer 2 ................................................................................................. 49 Auto-reload Mode ............................................................................................... 49 Programmable Clock Output .............................................................................. 50 Programmable Counter Array (PCA) ................................................ ...

  • Page 175

    USB Controller .................................................................................. 114 Introduction ....................................................................................................... 114 Description........................................................................................................ 115 Configuration .................................................................................................... 118 Read/Write Data FIFO ...................................................................................... 120 Bulk/Interrupt Transactions............................................................................... 121 Control Transactions......................................................................................... 125 Isochronous Transactions..................................................................................126 Miscellaneous ....................................................................................................128 Suspend/Resume Management ........................................................................129 Detach Simulation..............................................................................................131 USB Interrupt System ....................................................................................... 131 USB Registers ...

  • Page 176

    ... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...