adt7476a Analog Devices, Inc., adt7476a Datasheet - Page 25

• Manufacturer Part Number: adt7476a
• Description: Dbcool Remote Thermal Controller And Voltage Monitor
• Manufacturer: Analog Devices, Inc.

Figure 29 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are
referred to as sticky because they remain set until read by
software. This ensures that an out-of-limit event cannot be
missed if the software is periodically polling the device.
Note that:
•
•
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts,
it is recommend to handle the SMBALERT interrupt as follows:
1.
2.
3.
4.
5.
6.
7.
TEMPERATURE
STATUS BIT
HIGH LIMIT
SMBALERT
STICKY
The SMBALERT output remains low for the entire
duration that a reading is out-of-limit and until the
status register has been read. This has implications on
how software handles the interrupt.
THERM overtemperature events are not sticky. They reset
immediately after the overtemperature condition ceases.
Detect the SMBALERT assertion.
Enter the interrupt handler.
Read the status registers to identify the interrupt source.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (0x74 and 0x75).
Take the appropriate action for a given interrupt source.
Exit the interrupt handler.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 30.
Figure 29. SMBALERT and Status Bit Behavior
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
CLEARED ON READ
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Masking Interrupt Sources
Interrupt Mask Register 1 (0x74) and Interrupt Mask Register 2
(0x75) allow individual interrupt sources to be masked to
prevent SMBALERT interrupts. Note: Masking an interrupt
source prevents only the SMBALERT output from being
asserted; the appropriate status bit is set normally.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (V
Bit 1 (V
Bit 0 (2.5V) = 1, masks SMBALERT for 2.5V
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit masks
SMBALERT for a THERM event. If the TACH4 pin is being used
as GPIO6, setting this bit masks interrupts related to GPIO6.
STATUS BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
STICKY
Figure 30. How Masking the Interrupt Source Affects SMBALERT Output
CC
CCP
) = 1, masks SMBALERT for V
) = 1, masks SMBALERT for V
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
(TEMP BELOW LIMIT)
CC
CLEARED ON READ
CCP
(SMBALERT REARMED)
INTERRUPT MASK BIT
channel.
channel.
IN
/ THERM .
CLEARED
ADT7476A