qlx4270-dp Intersil Corporation, qlx4270-dp Datasheet - Page 3

• Manufacturer Part Number: qlx4270-dp
• Description: Displayport Lane Extender
• Manufacturer: Intersil Corporation

Pin Descriptions
Exposed Pad
PIN NAME
CP3[A,B,C]
CP4[A,B,C]
CP2[C,B,A]
CP1[C,B,A]
OUT4[N,P]
OUT3[N,P]
OUT2[N,P]
OUT1[N,P]
IN1[P,N]
IN2[P,N]
IN3[P,N]
IN4[P,N]
GND
V
IS1
IS2
IS4
IS3
DT
NC
DD
4, 7, 10, 29,
16, 17, 24
38, 45, 46
18, 19, 20
21, 22, 23
39, 40, 41
42, 43, 44
NUMBER
32, 35
11, 12
27, 28
30, 31
33, 34
36, 37
PIN
2, 3
5, 6
8, 9
13
14
15
25
26
1
-
3
Detection Threshold. Reference DC CURRENT threshold for input signal power detection. Data
output Out[k] is muted when the power of the equalized version of In[k] falls below the threshold.
Tie to ground to disable electrical idle preservation and always enable the limiting amplifier.
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
Ground
No-Connect
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Exposed ground pad. For proper electrical and thermal performance, this pad should be connected
to the PCB ground plane.
QLx4270-DP
DESCRIPTION
November 19, 2009
FN6972.1