qlx4270-dp Intersil Corporation, qlx4270-dp Datasheet - Page 5

• Manufacturer Part Number: qlx4270-dp
• Description: Displayport Lane Extender
• Manufacturer: Intersil Corporation

Control Pin Boost Setting
The voltages at the CP pins are used to determine the
boost level of each channel of QLx4270-DP. For each of
the four channels, k, the [A], [B], and [C] control pins
(CP[k]) are associated with a 3-bit non binary word.
While [A] can take one of two values, ‘LOW’ or ‘HIGH’,
[B] and [C] can take one of three different values: ‘LOW’,
‘MIDDLE’, or ‘HIGH’. This is achieved by changing the
value of a resistor connected between VDD and the CP
pin, which is internally pulled low with a 25kΩ resistor.
Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,
‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is
achieved with an open resistance. Table 1 defines the
mapping from the 3-bit CP word to the 18 out of 32
possible levels available via the serial interface on the
Evaluation Board kit.
Electrical Characteristics
NOTES:
Output Return Loss
(Com. to Diff.
Conversion)
Output Residual Jitter
Output Transition Time
Lane-to-Lane Skew
Propagation Delay
3. After channel loss, differential amplitudes at QLx4270-DP inputs must meet the input voltage range specified in “Absolute
4. Temperature = +25°C, V
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
6. Measured using a PRBS 2
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR
Maximum Ratings” on page 4.
signal (as measured at the input to the channel). Total jitter (TJ) is DJ
media-induced loss only.
CP[A]
RESISTANCE BETWEEN CP PIN
Open
Open
Open
Open
Open
Open
Open
Open
Open
0Ω
PARAMETER
AND QLx4270-DP BOOST LEVELS
AND V
CP[B]
Open
Open
Open
25kΩ
25kΩ
25kΩ
Open
0Ω
0Ω
0Ω
DD
SYMBOL
DD
7
5
S
-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
t
DC
r
, t
= 1.2V.
22
CP[C]
Open
25kΩ
Open
25kΩ
Open
25kΩ
Open
f
0Ω
0Ω
0Ω
V
DD
= 1.2V, T
50MHz to 1.35GHz
2.7Gb/s; Up to 2m 38AWG standard twin-axial
cable (11.5dB loss)
20% to 80%
From IN[k] to OUT[k]
SERIAL BOOST
LEVEL
A
= +25°C, and V
10
14
15
12
16
0
2
4
6
8
QLx4270-DP
CONDITION
If all four channels are to use the same boost level, then
a minimum number of board resistors can be realized by
tying together like CP[k][A,B,C] pins across all channels
k. For instance, all four CP[k][A] pins can be tied to the
same resistor running to VDD. Consequently, only three
resistors are needed to control the boost of all four
channels. If the CP Pins are tied together and the 25kΩ is
used, the value changes to a 3.125kΩ resistor because
the 25kΩ is divided by 4.
Channel Power-Down
The IS[k] pin powers down the equalizer channel when
pulled low. This feature allows individually to power down
unused channels and to minimize power consumption.
Example: for DisplayPort applications with 1 or 2 links,
the unused channels may be powered down to save
power. The current draw for a channel is reduced from
50mA to 3.8mA when powered down.
IN
TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR
CP[A]
= 800mV
RESISTANCE BETWEEN CP PIN
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
pp
+ 14.1 x RJ
AND QLx4270-DP BOOST LEVELS (Continued)
P-P
, unless otherwise noted. (Continued)
AND V
CP[B]
Open
Open
25kΩ
25kΩ
25kΩ
0Ω
0Ω
0Ω
RMS
MIN
DD
20
30
.
0.15
TYP
60
CP[C]
25kΩ
Open
25kΩ
Open
25kΩ
0Ω
0Ω
0Ω
MAX UNITS NOTES
100
500
0.2
50
SERIAL BOOST
November 19, 2009
dB
UI
ps
ps
ps
LEVEL
17
19
21
23
24
26
28
31
3, 5, 6
FN6972.1
4
7