pdi1394l21 NXP Semiconductors, pdi1394l21 Datasheet
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pdi1394l21 Summary of contents
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... NOTICE: SEE ATTACHED ERRATA (REVISED 8/23/2000) WHICH FOLLOWS THIS DOCUMENT FOR INFORMATION REGARDING CHANGED SPECIFICATIONS PDI1394L21 1394 full duplex AV link layer controller Preliminary specification Supersedes data of 2000 Jun 06 hilips Semiconductors INTEGRATED CIRCUITS 2000 Aug 24 ...
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... MPEG–2 and DVC codecs. An 80C51 compatible byte-wide host interface is provided for internal register configuration as well as performing asynchronous data transfers. The PDI1394L21 is powered by a single 3.3V power supply and the inputs and outputs are 5V tolerant available in the LQFP100 and TQFP100 packages. CONDITIONS MIN 3 ...
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... AV1 D5 76 AV1 D6 77 AV1 GND 80 AV2ERR1 81 AV2ERR0 82 AV2ENDPCK 83 AV2SYNC 84 AV2CLK 85 AV2FSYNC 86 AV2VALID 87 GND AV2 D0 90 AV2 D1 91 AV2 D2 92 AV2 D3 93 GND AV2D4 96 AV2 D5 97 AV2 D6 98 AV2 D7 99 AV2ENKEY 100 N/C SV00877 3 Preliminary specification PDI1394L21 ...
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... LINK CORE MEMORY (ISOCH & ASYNC PACKETS) ASYNC TRANSMITTER AND RECEIVER CONTROL AND STATUS REGISTERS 4 Preliminary specification PDI1394L21 SV00878 CYCLEOUT CYCLEIN PHY D[0:7] PHY CTL[0:1] LREQ ISO_N SCLK NOTE: THERE IS ONLY ONE ISOCHRONOUS RECEIVER AND ONE ISOCHRONOUS TRANSMITTER—THEREFORE, WHEN EITHER AVPORT IS SET ...
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... HIF CS_N, then a write cycle takes place. This can be used to connect CPUs that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the R/W_N line to the HIF WR_N and tie HIF RD_N LOW.) Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L21 27 HIF RD_N I internal registers is requested ...
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... Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more 54 LREQ O information. (Used to request arbitration or read/write PHY registers). 55 SCLK I System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency). 2000 Aug 24 NAME AND FUNCTION NAME AND FUNCTION NAME AND FUNCTION 6 Preliminary specification PDI1394L21 ...
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... Bushold and Link/PHY single capacitor galvanic isolation 9.4.1.1 Bushold The PDI1394L21 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw ...
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... The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 2000 Aug 24 NAME AND FUNCTION CONDITIONS CONDITIONS 1, 2 CONDITIONS CONDITIONS 8 Preliminary specification PDI1394L21 LIMITS UNIT UNIT MIN. MAX. 3.0 3 ...
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... Overview The PDI1394L21 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2 and DVC codecs. Via this interface, the AV Link maps and unmaps these AV datastreams from these codecs onto 1394 isochronous bus packets ...
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... This makes the internal updating automatic for quadlet reading. 3. Reading the bytes of the read shadow register can be done in any order and as often as needed. 2000 Aug 24 MUX Preliminary specification PDI1394L21 REGISTERS 32 SV00803 ...
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... With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the read shadow register. Once the data is copied into the read shadow register longer available in the queue itself so the CPU should always read all 4 bytes before attempting any other read access (be careful with interrupt handlers for the PDI1394L21!). 2000 Aug 24 ...
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... HIF D0..HIF D7 Figure 5. Write cycle signal timing (2 independent write cycles) 12.4 The Asynchronous Packet Interface The PDI1394L21 provides an interface to asynchronous data packets through the registers in the host interface. The format of the asynchronous packets is specified in the following sections. 12.4.1 Reading an Asynchronous Packet Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK) register ...
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... Block write requests Block read responses Lock requests Lock responses Concatenated self-ID / PHY packets 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow 0 spd tLabel rt tCode destinationID rCode 13 Preliminary specification PDI1394L21 TRANSACTION CODE (tCode hex E hex 0000 SV00250 0000 SV00249 ...
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... Figure 8. Quadlet Write Request Transmit Format 2000 Aug 24 Description 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow quadlet data 14 Preliminary specification PDI1394L21 0000 SV00251 ...
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... Figure 10. Block Read Request Transmit Format See Table 1. For quadlet write requests and quadlet read responses, this field holds the data to be transferred. The number of bytes requested in a block read request. 15 Preliminary specification PDI1394L21 0000 SV00252 0000 SV00253 Description ...
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... Figure 12. Block Read or Lock Response Transmit Format 2000 Aug 24 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow dataLength extendedTcode Block data padding (if needed) Figure 11. Block Packet Transmit Format 0 spd tLabel rt tCode destinationID rCode dataLength extendedTcode Block data padding (if needed) 16 Preliminary specification PDI1394L21 0000 SV00254 0000 SV00255 ...
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... Quadlet read requests Quadlet/block write responses Qaudlet write requests Quadlet read responses Block read requests Block write requests Block read responses Lock requests Lock responses Concatenated self-ID / PHY packets Confirmation of packet transmission 17 Preliminary specification PDI1394L21 0000 SV00256 TRANSACTION CODE ...
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... Upon receipt of a broadcast packet, if any ACK code other than ACK_DATA_ERROR is produced, asume packet receipt was OK. ACK_DATA ERROR indicates the packet was received with an error, appropriate steps should be taken to ignore the packet and inform the sending node of the error. 2000 Aug 24 Description Description 18 Preliminary specification PDI1394L21 ...
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... Aug 24 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow spd destinationID tLabel rt tCode sourceID rCode spd Figure 15. Write Response Receive Format 19 Preliminary specification PDI1394L21 priority ackSent SV00257 priority u ackSent SV00258 ...
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... Figure 17. Quadlet Read Response Receive Format 2000 Aug 24 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow quadlet data spd destinationID tLabel rt tCode sourceID rCode quadlet data spd 20 Preliminary specification PDI1394L21 priority ackSent SV00259 priority u ackSent SV00260 ...
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... Figure 19. Block Write or Lock Request Receive Format 2000 Aug 24 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow data length spd Figure 18. Block Read Request Receive Format destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow dataLength extendedTcode Block data padding (if needed) spd 21 Preliminary specification PDI1394L21 priority ackSent SV00261 priority ackSent SV00262 ...
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... Aug 24 destinationID tLabel rt tCode sourceID rCode dataLength extendedTcode Block data padding (if needed) spd 1110 self ID packet data 00 Figure 21. Self-ID Receive Format 22 Preliminary specification PDI1394L21 priority u ackSent SV00263 0000 2 2 ackSent SV00264 ...
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... For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV layer logic. 2000 Aug 24 1110 PHY packet first quadlet Figure 22. PHY Packet Receive Format destinationID tLabel 00 1000 2 23 Preliminary specification PDI1394L21 0000 2 2 SV00265 conf 2 SV00821 ...
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... Interrupts The PDI1394L21 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers; ...
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... A bit/field with a name in it and light shading is a READ ONLY (status) bit/field. A one bit value ( written at the bottom of a writeable (control) bit is the default value after power-on-reset. Table 8. Full Bitmap of all Registers (consists of three tables shown on the following pages) 2000 Aug 24 25 Preliminary specification PDI1394L21 ...
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... DBS FN QPC FDF Preliminary specification PDI1394L21 VERSION CODE 1 1 ATACK CYCLE_OFFSET ...
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... Aug TAG CHANNEL DBS FN QPC FDF SPD TAG CHANNEL Preliminary specification PDI1394L21 SPD BPAD SYT ...
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... LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE (WRITE ONLY) QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER) QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER Preliminary specification PDI1394L21 TOF ...
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... Bit 11: R/W Cycle Master (CYMASTER): When asserted and the PDI1394L21 is attached to the root PHY (ROOT bit = 1), and the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle Master function in such a case, first reset CYMASTER, then set it again ...
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... Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays asserted until the isochronous cycle has ended. Bit 0: R/W Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only occurs when cycle master is not asserted. 2000 Aug 24 SV00893 30 Preliminary specification PDI1394L21 ...
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... PHYRGAD Reset Value 0x00000000 Bit 31: R/W Read Phy Chip Register (RDPHY): When asserted, the PDI1394L21 sends a read register request with address equal to Phy the Phy interface. This bit is cleared when the request is sent. Bit 30: R/W Write Phy Chip Register (WRPHY): When asserted, the PDI1394L21 sends a write register request with address equal to Phy the Phy interface ...
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... AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register. Bit Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register. Bit 0: R Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register. 2000 Aug SV00857 32 Preliminary specification PDI1394L21 ...
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... HIGH for at least the duration of one AVxCLK period. Failure may cause the application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes will be flushed from the FIFO and transmission will cease immediately. 2000 Aug 24 TRDEL MAXBL PM 33 Preliminary specification PDI1394L21 SV00886 ...
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... AVFSYNCIN has been detected or all ‘1’ such edge was detected since the previous packet. The upper 8 bits of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status Register is unset (=0), the full 24 bits can be set to any application specified value. 2000 Aug 24 DBS FN QPC SV01747 FN . FDF SYT SV00281 34 Preliminary specification PDI1394L21 ...
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... These are the enabled bits for the AV Transmitter Control Reset Value 0x00000000 Bits 9..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK). 2000 Aug 24 SV00882 SV00891 35 Preliminary specification PDI1394L21 ...
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... ODD/EVEN bit accompany each application packet sent for the purpose of changing “keys” after short intervals of time (makes breaking an encryption code more difficult). The PDI1394L21 uses the sync field ODD/EVEN bit for this purpose. Data is inputted to the transmitting AV port accompanied by the state of the ODD/EVEN bit presented to the AVx ENKEY pin. The pin state at the rising edge of the AVCLK as the first byte of the packet determines the ODD/EVEN “ ...
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... AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration of one AVCLK period. Failure may cause the application interface of this module to be improperly reset (or not reset at all). 2000 Aug 24 BPAD SV00887 37 Preliminary specification PDI1394L21 ...
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... CIPTAGFLT: Faulty CIP header tag (E,F bits). i.e.: The CIP header did not meet the standard and the whole packet is ignored. Bit 1: R/W RCVBP: Bus packet processing complete. Bit 0: R/W SQOV: Status queue overflow. This is a fatal error, the recommended action is to reset and re-initialize the receiver. 2000 Aug 24 DBS FN QPC FMT FDF SYT 38 Preliminary specification PDI1394L21 SV00286 SV00287 SV00881 ...
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... SYNC: Last received SY code in isochronous bus packet header. Bit 1 is odd/even encryption bit key. State of this bit will be outputted at active (receiving) AVPORT on the AVxENKEY pin while the accompanying application packet is being outputted. Also see Section 13.2.6 for a description of the operation of this bit.. 2000 Aug 24 SV00888 SPD TAG CHANNEL ERR SV01017 39 Preliminary specification PDI1394L21 ...
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... Bit 3: R IRXMF: Full: no space available. Bit 2: R IRXMAF: Almost full: exactly one quadlet of storage available. Bit 1: R IRXM5AV: At least 5 more quadlets of storage available. Bit 0: R RXME: Memory bank is empty (no data committed). 2000 Aug full Preliminary specification PDI1394L21 SV00917 ...
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... TREQQF: Transmitter request queue full. Bit 2: R TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available). Bit 1: R TREQQ5AV: Transmitter request queue at least 5 quadlets available. Bit 0: R TREQQE: Transmitter request queue empty. 2000 Aug 24 MAXRC TOS TOF SV00889 SV00918 41 Preliminary specification PDI1394L21 ...
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... Bit 31..0: W TX_RP_LAST: Last quadlet of packet for transmitter response queue (write only). Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue. 2000 Aug 24 TX_RQ_NEXT SV00293 TX_RQ_LAST SV00294 TX_RP_NEXT SV00295 TX_RP_LAST SV00296 42 Preliminary specification PDI1394L21 ...
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... TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt. Bit 1: R/W TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt. 2000 Aug 24 RREQ RRSP Preliminary specification PDI1394L21 SV00297 SV00298 ...
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... 0 0 – 0 – 0 2.4 0.4 2.4 0.4 1 200 5 200 75 44 Preliminary specification PDI1394L21 SV00797 UNIT NOTE V Pin categories Pin categories Pin categories LOW to HIGH transition Pin categories HIGH to LOW transition Pin category 1 ...
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... Figure 28 Note 20pF Figure 29 L Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 30 Figure 31 Figure 31 Figure 31 Figure 32 Figure 33 45 Preliminary specification PDI1394L21 Category 7: Category 8: LREQ SCLK LIMITS +70 C UNIT amb MIN TYP MAX 41. ...
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... ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR Figure 25. AV Interface Operation Diagram t t WHIGH WLOW É É É t PERIOD É É É VALID t OD Figure 26. AV Interface Timing Diagram t PWFS Figure 27. AVxFSYNC Timing Diagram 46 Preliminary specification PDI1394L21 INVALID DATA MESSAGE SV00240 SV00688 SV00890 ...
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... SV00694 VALID É É É É É É É É É É É É É É É É É É t ACC t WRP VALID Figure 30. Host Interface Timing Waveforms 47 Preliminary specification PDI1394L21 50% SV00919 VALID SV00920 ...
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... AV link layer controller 16.5 CYCLEIN/CYCLEOUT Timings CYCLEIN SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 2000 Aug 24 50% 50% 50 CWH CWL t CP Figure 31. CYCLEIN Waveform 50 50% Figure 32. CYCLEOUT Waveforms 50% 50% t RESET SV00698 Figure 33. RESET_N Waveform 48 Preliminary specification PDI1394L21 SV00696 50 50% SV00697 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller TQFP100: plastic thin quad flat package; 100 leads; body 1.0 mm 2000 Aug 24 49 Preliminary specification PDI1394L21 SOT386-1 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller LQFP100: plastic low profile quad flat package; 100 leads; body 1.4 mm 2000 Aug 24 50 Preliminary specification PDI1394L21 SOT407-1 ...
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... Read Request Queue. Refer to section 12.5.2.4 (Self-ID and PHY packets receive) in the “PDI1394L21 1394 Full Duplex AV Link Layer Controller” data sheet for the proper format of a self-ID packet. Description of observed behavior: Occasionally 0x000000E0 and 0x00000010 quadlets are found in the Read Request Queue with no accompanying self-ID and acknowledge quadlet ...
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... L21 (SYSCLK, CTL0, CTL1, D0...D7 pull-down device. The slight additional pin to ground current will set the proper pin state at the release of reset. Errata To the PDI1394L21 1394 Full Duplex AV Link Layer Controller (Data Sheet dated: 2000 August 24). resistor at each capacitor coupled link / PHY interface input and I/O pin ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 2000 Aug 24 NOTES 53 Preliminary specification PDI1394L21 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Aug 24 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 54 Preliminary specification PDI1394L21 All rights reserved. Printed in U.S.A. Date of release: 08-00 9397 750 07446 ...