pdi1394l21 NXP Semiconductors, pdi1394l21 Datasheet - Page 29

• Manufacturer Part Number: pdi1394l21
• Description: 1394 Full Duplex Av Link Layer Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.1 Link Control Registers
13.1.1
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
Reset Value 0xFFFF0101
Bit 31..22:
Bit 21..16:
Bit 15..8:
Bit 7..0:
13.1.2 General Link Control (LNKCTL) – Base Address: 0x004
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
Reset Value 0x46000002
Bit 31:
Bit 30:
Bit 29..27:
Bit 26:
Bit 25:
Bit 21:
Bit 20:
Bit 12:
Bit 11:
2000 Aug 24
1394 full duplex AV link layer controller
ID Register (IDREG) – Base Address: 0x000
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
PART CODE: “01” designates PDI1394L21.
VERSION CODE: “02” shows this is revision level 2 of this part.
IDValid (IDVALID): When equal to one, the PDI1394L21 accepts the packets addressed to this node. This bit is
automatically set after selfID complete and node ID is updated.
Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the
bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30
also enables the reception of PHY configuration packets in the asynchronous request queue.
Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is
defined below:
Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.
Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.
Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.
Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.
Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified
isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified
cycles, a “0” accepts isochronous packets sent outside the specified cycle.
Cycle Master (CYMASTER): When asserted and the PDI1394L21 is attached to the root PHY (ROOT bit = 1), and
the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master
function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle
Master function in such a case, first reset CYMASTER, then set it again.
31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSYCTRL
3130
000 = use protocol requested by received packet (either dual phase or single phase)
001 = send busy A when it is necessary to send a busy acknowledge (testing/diagnostics)
010 = send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics)
011 = use single phase retry protocol
100 = use protocol requested in packet, always send a busy ack (for all packets)
101 = busy A all incoming packets
110 = busy B all incoming packets are ‘1’
111 = use single phase retry protocol, always send a busy ack
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS ID
NODE ID
29
PART CODE
VERSION CODE
SV00915
SV00892
ATACK
PDI1394L21
Preliminary specification