74F564PC Fairchild Semiconductor, 74F564PC Datasheet
74F564PC
Specifications of 74F564PC
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74F564PC Summary of contents
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... Package Number 74F564SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F564PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © ...
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Unit Loading/Fan Out Pin Names D –D Data Inputs Clock Pulse Input (Active Rising Edge) OE 3-STATE Output Enable Input (Active LOW) O –O 3-STATE Outputs 0 7 Functional Description The 74F564 consists of eight edge-triggered flip-flops ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ AC Operating Requirements Symbol Parameter t ...
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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...