is42s16160a-6tl Integrated Silicon Solution, Inc., is42s16160a-6tl Datasheet - Page 17

• Manufacturer Part Number: is42s16160a-6tl
• Description: 256 Mb Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S83200A
IS42S16160A
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
WRITE
A WRITE command can be issued to any active bank.
The start address is specified by A0-9(x8), A0-8(x16).
1st input data is set at the same cycle as the WRITE.
The consecutive data length to be write is defined
by the Burst Length. The address sequence of
burst data is defined by Burst Type. Minmum delay
time of a WRITE command after an ACT command to
the same bank is tRCD. From the last input data to the
PRE command , the write recovery time (tWR) is
A0-9,11-12
A0-9,11-12
Command
Command
BA0-1
BA0-1
CLK
A10
CLK
A10
DQ
DQ
ACT
ACT
Xa
00
Xa
Xa
Xa
00
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
tRCD
tRCD
Write
Write
Da0
Da0
Ya
00
Ya
00
0
Write with Auto-Precharge (BL=4)
1
Da1
Da1
Write (BL=4)
Da2
Da2
BL
BL
Da3
Da3
required. When A10 is high at a WRITE command ,
auto-precharge (WRITEA) is performed. Any com-
mand (READ,WRITE,PRE,ACT,TBST) to the same
bank is inhibited till the internal precharge is complete.
The internal precharge starts at tWR after the last input
data cycle . The next ACT command can be issued
after (BL+tWR-1+tRP) from the previous WRITEA. In
any case, tRCD+BL+tWR-1
internal precharge starts
tWR
tWR
PRE
0
tRP
tRP
ACT
ACT
Xa
Xa
Xa
Xa
00
00
tRASmin must be met.
ISSI
17
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