is42s16100f-7tla1 Integrated Silicon Solution, Inc., is42s16100f-7tla1 Datasheet

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is42s16100f-7tla1

Manufacturer Part Number
is42s16100f-7tla1
Description
512k Words X 16 Bits X 2 Banks 16mb Sdram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
IS42/45S16100F, IS42VS16100F
FEATURES
• Clock frequency:
• Fully synchronous; all signals referenced to a
• Two banks can be operated simultaneously and
• Dual internal bank controlled by A11
• Single power supply:
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and
• Byte controlled by LDQM and UDQM
• Packages 400-mil 50-pin TSOP-II and 60-ball
• Lead-free package option
• Available in Industrial Temperature
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
06/03/2010
512K Words x 16 Bits x 2 Banks
16Mb SDRAM
IS42/45S16100F: 200, 166, 143 MHz
IS42VS16100F: 133, 100 MHz
positive clock edge
independently
(bank select)
IS42/45S16100F: V
IS42VS16100F: V
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
precharge command
BGA
dd
dd
/V
/V
ddq
ddq
= 1.8V
= 3.3V
DESCRIPTION
ISSI
IS45S16100F and IS42VS16100F are each organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All
inputs and outputs signals refer to the rising edge of the
clock input.
ADDRESS TABLE
KEY TIMING PARAMETERS
Parameter
Power Supply V
Refresh Count
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
Parameter
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from
Clock
CAS Latency = 3
CAS Latency = 2
Notes:
1. Available for IS42S16100F only
2. Available for IS42S16100F and IS45S16100F only
3. Available for IS42VS16100F only
’s 16Mb Synchronous DRAM IS42S16100F,
dd
/V
ddq
-5
200
100
10
5
5
6
(1)
PRELIMINARY INFORMATION
IS42/45S16100F
166
100
-6
5.5
10
6
6
(2)
2K/32ms
3.3V
-7
143
100
5.5
10
7
6
(2)
JUNE 2010
A0-A10
A0-A7
-75
133
100
A10
A11
7.5
10
6
8
(3)
IS42VS16100F
-10
2K/32ms
100
10
12
83
7
8
1.8V
(3)
Unit
Mhz
Mhz
ns
ns
ns
ns
1

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