is42s16100c1-die Integrated Silicon Solution, Inc., is42s16100c1-die Datasheet

is42s16100c1-die

Manufacturer Part Number

is42s16100c1-die

Description

512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram

Manufacturer

Integrated Silicon Solution, Inc.

Datasheet

1.IS42S16100C1-DIE.pdf (1 pages)

Current page: 1 of 1
Download datasheet (36Kb)

IS42S16100C1-DIE

FEATURES

• Clock frequency: 143 MHz

• Power supply: 3.3V

• Fully synchronous; all signals referenced to a

• Two banks can be operated simultaneously and

• Dual internal bank controlled by A11

• Programmable burst length

• Programmable burst sequence:

• 2048 refresh cycles every 32 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and

• Byte controlled by LDQM and UDQM

• Pads located along edges

PIN DESCRIPTIONS

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. 00A

11/18/05

512K Words x 16 Bits x 2 Banks (16-MBIT)

SYNCHRONOUS DYNAMIC RAM

A0-A11

A0-A10

A11

A0-A7

DQ0 to DQ15

CLK

CKE

RAS

CAS

positive clock edge

independently

(bank select)

– (1, 2, 4, 8, full page)

Sequential/Interleave

operations capability

precharge command

Address Input

Row Address Input

Bank Select Address

Column Address Input

Data DQ

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

Write Enable

1-800-379-4774

DESCRIPTION

ISSI

organized as a 524,288-word x 16-bit x 2-bank for

improved performance. The synchronous DRAMs

achieve high-speed data transfer using pipeline

architecture. All inputs and outputs signals refer to the

rising edge of the clock input. Note: This is a summary

datasheet specific to the die format. Please refer to the

IS42S16100C1 for complete device specification.

KEY TIMING PARAMETERS

BONDING DIAGRAM

LDQM

UDQM

VDD

GND

VDDQ

GNDQ

Parameter

Clock Cycle Time

Clock Frequency

Access Time from Clock

’s 16Mb Synchronous DRAM IS42S16100C1 is

CAS Latency = 3

CAS Latency = 2

CAS Latency = 3

CAS Latency = 2

CAS Latency = 3

CAS Latency = 2

Laser Alignment Mark

Lower Bye, Input/Output Mask

Upper Bye, Input/Output Mask

Power

Ground

Ground for DQ Pin

No Connection

Power Supply for DQ Pin

ADVANCED INFORMATION

NOVEMBER 2005

ISSI

143

125

5.5

6.0

LOGO

-7

MHz

Unit

Related parts for is42s16100c1-die

Related keywords

is42s16100c1-die datasheet
is42s16100c1-die data sheet
is42s16100c1-die pdf datasheet
is42s16100c1-die component
is42s16100c1-die part
is42s16100c1-die distributor
is42s16100c1-die RoHS
is42s16100c1-die datasheet download