is42s16100c1 Integrated Silicon Solution, Inc., is42s16100c1 Datasheet - Page 32

• Manufacturer Part Number: is42s16100c1
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

32
IS42S16100C1
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
WDL
) from the precharge command to the point
CLK
DQ
DQM
CLK
DQ
WRITE (CA=A, BANK 0)
WRITE A0
D
WRITE (CA=A, BANK 0)
IN
A0
WRITE A0
D
IN
D
IN
A0
A1
D
IN
D
Integrated Silicon Solution, Inc. — www.issi.com —
IN
A1
A2
D
IN
D
IN
A2
t
A3
DPL
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
PRECHARGE (BANK 0)
D
PRE 0
CAS
CAS
CAS Latency
CAS
CAS
PRE 0
IN
A3
MASKED BY DQM
t
t
WDL
PRECHARGE (BANK 0)
DPL
t
WDL
=0
DPL
) has elapsed. Therefore, the
3
0
1
ISSI
1-800-379-4774
2
0
1
11/03/06
Rev. D
®