is42s16400f-5tli Integrated Silicon Solution, Inc., is42s16400f-5tli Datasheet - Page 35

• Manufacturer Part Number: is42s16400f-5tli
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
IS42S16400F, IC42S16400F
IS45S16400F
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/08
A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out appearing CAS latency
later. The PRECHARGE to bank n will begin after t
is met, where t
registered.The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
Internal States
COMMAND
ADDRESS
Internal States
COMMAND
ADDRESS
BANK m
BANK n
BANK m
BANK n
CLK
DQ
CLK
DQ
wr
begins when the READ to bank m is
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
BANK n,
BANK n
WRITE - AP
T1
COL a
BANK n,
D
Page Active
T1
BANK n
COL a
D
IN
WRITE with Burst of 4
IN
a
a
Page Active
WRITE with Burst of 4
D
T2
NOP
T2
D
IN
NOP
IN
a+1
a+1
READ - AP
wr
BANK m,
BANK m
T3
COL b
T3
D
NOP
Interrupt Burst, Write-Back
IN
a+2
t
CAS Latency - 3 (BANK m)
WR
4.Interrupted by a WRITE (with or without auto precharge):
- BANK n
AWRITE to bank m will interrupt a WRITE on bank n when
registered.The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
wr
WRITE - AP
T4
NOP
BANK m,
BANK m
T4
COL b
D
is met, where t
READ with Burst of 4
Interrupt Burst, Write-Back
IN
b
t
WR
WRITE with Burst of 4
- BANK n
T5
NOP
T5
D
NOP
IN
b+1
wr
begins when the WRITE to bank
T6
NOP
T6
D
NOP
D
Precharge
IN
t
OUT
RP - BANK n
b+2
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
NOP
D
T7
D
NOP
Precharge
OUT
Write-Back
IN
t
RP - BANK m
b+3
t
b+1
RP - BANK m
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