is42s16400f-5tli Integrated Silicon Solution, Inc., is42s16400f-5tli Datasheet - Page 6

• Manufacturer Part Number: is42s16400f-5tli
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16400F, IC42S16400F
IS45S16400F
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(t
required for a single refresh operation, and no other com-
mands can be executed during this period. This command is
executed at least 4096 times every 64ms. During an AUTO
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are gen-
erated automatically internally. SELF REFRESH can be
used to retain data in the SDRAM without external clocking,
even if the rest of the system is powered down. The SELF
REFRESH operation is started by dropping the CKE pin
from HIGH to LOW. During the SELF REFRESH operation
all other inputs to the SDRAM become “Don’t Care”. The
device must remain in self refresh mode for a minimum
period equal to t
for an indefinite period beyond that.The SELF-REFRESH
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The next command cannot be executed until the device
internal recovery period (t
goes HIGH, the NOP command must be issued (minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
6
ras
or may remain in self refresh mode
rc
) has elapsed. Once CKE
rc
) is
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
Integrated Silicon Solution, Inc. — www.issi.com
05/29/08
Rev. C