is42vs16100d Integrated Silicon Solution, Inc., is42vs16100d Datasheet

is42vs16100d

Manufacturer Part Number

is42vs16100d

Description

512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram

Manufacturer

Integrated Silicon Solution, Inc.

Datasheet

1.IS42VS16100D.pdf (1 pages)

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IS42VS16100D-DIE

512K Words x 16 Bits x 2 Banks (16-MBIT)

SYNCHRONOUS DYNAMIC RAM

FEATURES

• Clock frequency: 135, 100, 83 MHz

•

PIN DESCRIPTIONS

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. 00B

07/01/05

A0-A11

A0-A10

A11

A0-A7

DQ0 to DQ15

CLK

CKE

RAS

CAS

Power Supply: 1.8V

Fully synchronous; all signals referenced to a

positive clock edge

Two banks can be operated simultaneously and

independently

Dual internal bank controlled by A11 (bank

select)

Programmable burst length (1, 2, 4, 8, full page)

Programmable burst sequence: Sequential/

Interleave

Programmable full and half drive strength

Programmable CAS latency (2, 3 clocks)

2048 refresh cycles every 32 ms

Random column address every clock cycle

Burst read/write and burst read/single write

operations capability

Byte controlled by LDQM and UDQM

Auto Refresh and Self Refresh modes

Partial Array Self-Refresh

Power Down and Deep Power Down

Pads located along edges of die

Address Input

Row Address Input

Bank Select Address

Column Address Input

Data DQ

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

1-800-379-4774

DESCRIPTION

ISSI

organized as a 524,288-word x 16-bit x 2-bank for

improved performance. The synchronous DRAMs

achieve high-speed data transfer using pipeline

architecture. All inputs and outputs signals refer to the

rising edge of the clock input. Note: This is a summary

datasheet specific to the die format. Please refer to the

IS42VS16100D datasheet for complete device

specifications.

KEY TIMING PARAMETERS

BONDING DIAGRAM

LDQM

UDQM

Vss

Parameter

Clock Cycle Time

Clock Frequency

Access Time from Clock

DDQ

SSQ

’s 16Mb Synchronous DRAM IS42VS16100D is

CAS Latency = 3

CAS Latency = 2

CAS Latency = 3

CAS Latency = 2

CAS Latency = 3

CAS Latency = 2

NC NC

Write Enable

Lower Bye, Input/Output Mask

Upper Bye, Input/Output Mask

Power

Ground

Power Supply for DQ Pin

Ground for DQ Pin

No Connection

ADVANCED INFORMATION

LOGO

ISSI

JULY 2005

-7.5

133

100

7.4

100

-10

MHz

Unit

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