is42vs16100e Integrated Silicon Solution, Inc., is42vs16100e Datasheet
is42vs16100e
Manufacturer Part Number
is42vs16100e
Description
512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42VS16100E.pdf
(1 pages)
Available stocks
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Company:
Part Number:
is42vs16100e-75TLI
Manufacturer:
ISSI
Quantity:
943
IS42VS16100E-DIE
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 133, 100, 83 MHz
• Power Supply: 1.8V
• Fully synchronous; all signals referenced to a
• Two banks can be operated simultaneously and
• Dual internal bank controlled by A11 (bank se-
• Programmable burst length (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/In-
• Programmable full and half drive strength
• Programmable CAS latency (2, 3 clocks)
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Burst read/write and burst read/single write op-
• Byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh modes
• Partial Array Self-Refresh
• Power Down and Deep Power Down
• Pads located along edges of die
PIN DESCRIPTIONS
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00D
11/14/07
A0-A11
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
positive clock edge
independently
lect)
terleave
erations capability
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
1-800-379-4774
DESCRIPTION
ISSI
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input. Note: This is a summary
datasheet specific to the die format. Please refer to
the IS42VS16100E datasheet for complete device
specifications.
KEY TIMINg PARAMETERS
BONDINg DIAgRAM
WE
LDQM
UDQM
V
Vss
V
V
NC
Parameter
Clock Cycle Time
Clock Frequency
Access Time from Clock
dd
ddq
ssq
’s 16Mb Synchronous DRAM IS42VS16100E is
X
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
15
Bonding Pads
10
16
PRELIMINARY INFORMATION
20
5
Burn-in Pads
25
1
NOVEMBER 2007
LOGO
LOGO
50
LOGO
-7.5
133
100
7.5
10
6
8
45
30
100
40
-10
10
12
83
7
8
35
(0,0)
Y
MHz
MHz
Unit
ns
ns
ns
ns
1
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