is64wv5128bls Integrated Silicon Solution, Inc., is64wv5128bls Datasheet - Page 15

• Manufacturer Part Number: is64wv5128bls
• Description: 512k X 8 High-speed Asynchronous Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

WRITE CYCLE NO. 3
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE NO. 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
03/04/2008
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE > V
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
WE
D
D
OE
OE
CE
CE
IN
IN
LOW
LOW
LOW
t
SA
(1,2)
(WE Controlled: OE is LOW During Write Cycle)
t
DATA UNDEFINED
DATA UNDEFINED
SA
(WE Controlled: OE is HIGH During Write Cycle)
Ih
.
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
15