lh28f016sct-zr Sharp Microelectronics of the Americas, lh28f016sct-zr Datasheet - Page 14

• Manufacturer Part Number: lh28f016sct-zr
• Description: Flash Memory 16mbit 2mbitx8
• Manufacturer: Sharp Microelectronics of the Americas

NOTES:
1. BUS operations are defined in Table 3.
2. X=Any valid address within the device.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and
5. If the block is locked, RP# must be at V
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP# must be at V
8. If the master lock-bit is set, RP# must be at V
9. Commands other than those shown above are reserved by SHARP for future device implementations and
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Byte Write
Block Erase and Byte Write
Suspend
Block Erase and Byte Write
Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
master lock codes. See Section 4.2 for read identifier code data.
block erase or byte write to a locked block while RP# is V
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is V
simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can
be done while RP# is V
should not be used.
Command
IH
.
Bus Cycles
Req’d.
≥2
1
2
1
2
2
1
1
2
2
2
Table 4. Command Definitions
HH
Notes
5,6
4
5
5
5
7
7
8
to enable block erase or byte write operations. Attempts to issue a
HH
HH
LHF16CZR
Oper
to set a block lock-bit. RP# must be at V
to clear block lock-bits. The clear block lock-bits operation
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(1)
First Bus Cycle
IH
.
Addr
WA
BA
BA
X
X
X
X
X
X
X
X
(2)
(9)
Data
FFH
B0H
D0H
90H
70H
50H
20H
60H
60H
60H
40H
10H
or
(3)
IH
Oper
Read
Read
Write
Write
Write
Write
Write
.
Second Bus Cycle
(1)
HH
to set the master
Addr
WA
BA
BA
IA
X
X
X
(2)
Data
Rev. 1.2
SRD
D0H
D0H
F1H
01H
WD
ID
(3)
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