lh28f016sct-zr Sharp Microelectronics of the Americas, lh28f016sct-zr Datasheet - Page 26

• Manufacturer Part Number: lh28f016sct-zr
• Description: Flash Memory 16mbit 2mbitx8
• Manufacturer: Sharp Microelectronics of the Americas

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP
accommodate
Three-line control provides for:
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory
deselected memory devices are in standby mode.
RP#
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# and Block Erase, Byte Write,
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte write
and lock-bit configuration completion. It transitions
low after block erase, byte write, or lock-bit
configuration commands and returns to V
the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
and Lock-Bit Configuration Polling
should
devices
provides
be
multiple
have
connected
three
memory
active
control
to
outputs
the
connections.
inputs
OH
system
when
while
LHF16CZR
to
RY/BY# is also V
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a 0.1µF ceramic capacitor
connected between its V
V
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7µF electrolytic capacitor should be placed at the
array’s power supply connection between V
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 V
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V
The V
writing and block erasing. Use similar trace widths
and layout considerations given to the V
bus. Adequate V
decrease V
PP
and GND. These high-frequency, low inductance
PP
PP
pin supplies the memory cell current for byte
PP
Trace on Printed Circuit Boards
voltage spikes and overshoots.
PP
OH
supply traces and decoupling will
when the device is in block erase
CC
and GND and between its
PP
Power supply trace.
CC
Rev. 1.2
CC
power
and
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