m58wr032et STMicroelectronics, m58wr032et Datasheet - Page 22

• Manufacturer Part Number: m58wr032et
• Description: 32 Mbit 2mb X 16, Multiple Bank, Burst 1.8v Supply Flash Memory
• Manufacturer: STMicroelectronics

M58WR032ET, M58WR032EB
If the Program and Verify Phase has successfully
completed the memory returns to Read mode. If
the P/E.C. fails to program and reprogram a given
Table 7. Factory Program Commands
Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.
22/81
Bank Erase
Double Word Program
Quadruple Word Program
Program
Command
Quadruple
Enhanced
Enhanced
Program
Factory
Factory
(5,6)
2. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1.
3. Address can remain Starting Address WA1 or be incremented.
4. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
5. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
6. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and
7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent
8. Any address within the bank can be used.
9. Any address within the block can be used.
check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.
Words in each Page can be written to any address.
(6)
Setup,
Program
Verify, Exit
Setup,
first Load
First
Program &
Verify
Subsequent
Loads
Subsequent
Program &
Verify
Exit
Phase
(4)
(5)
2+n
n+1 WA1
+1
2
3
5
5
4
1
BKA or
WA1
BKA or
WA1
BKA or
WA1
BKA or
WA1
WA1i
NOT
WA1
Add
BKA
(2)
(2)
(8)
(8)
(8)
(2)
(8)
1st
FFFFh
Data
PD1i
PD1
80h
35h
56h
30h
75h
WA1
WA2
WA1
BA or
WA2i
WA1
WA1
Add
BKA
(7)
(9)
(3)
(2)
2nd
Data
PD2i
PD1
PD1
PD2
PD1
D0h
D0h
location, the error will be signaled in the Status
Register.
Bus Write Operations
WA1
WA3
WA2
WA3i
WA2
WA2
Add
(7)
Automatic
Automatic
(2)
(3)
(7)
3rd
Data
PD3i
PD2
PD2
PD1
PD3
PD2
WAn
WAn
WA3
WA3
Add
Final -1
(3)
(3)
(7)
Data
PD3
PD3 WA4
PAn
PAn
WA1
WA1
WA4i
WA4
NOT
NOT
Add
(7)
(2)
(2)
(7)
Final
FFFFh
FFFFh
Data
PD4i
PD4
PD4