lm5034mtcx National Semiconductor Corporation, lm5034mtcx Datasheet - Page 15

• Manufacturer Part Number: lm5034mtcx
• Description: High Voltage Dual Interleaved Current Mode Controller With Active Clamp
• Manufacturer: National Semiconductor Corporation

Drivers Off, V
Off signal to disable the output drivers, connect the SS1,
SS2, COMP1, COMP2 and RES pins to ground, and enable
the 50 µA Soft-start current sources.
If the V
6.2V , the UVT comparator activates only the Drivers Off
signal. The output drivers are disabled but the V
is not disabled. Additionally, the CS1, CS2, SS1, SS2,
COMP1, COMP2 and RES pins are internally grounded, and
the 50 µA Soft-start current sources are enabled.
Oscillator
The oscillator frequency is set with an external resistor R
connected between the RT/SYNC and GND1 pins. The re-
sistor value is calculated from:
where F
mum of 2 MHz), and R
driver outputs (OUT1 and OUT2) switch at half the oscillator
frequency and 180˚ out of phase with each other. The volt-
age at the R
R
LM5034 with short direct connections to the pins.
The LM5034 can be synchronized to an external clock by
applying a narrow clock pulse to the R
Applications Information section for details on this proce-
dure. The R
lator is free running or externally synchronized.
PWM Comparator/Slope
Compensation
The PWM comparator of each controller compares a slope
compensated current ramp signal with the loop error voltage
derived from the COMP pin. The COMP voltage is typically
T
resistor should be located as close as possible to the
CC
S
voltage falls below the under-voltage threshold of
is the desired oscillator frequency in kHz (maxi-
T
T
/SYNC pin is internally regulated at 2.0V. The
resistor is always required, whether the oscil-
T
CC
is in kΩ. See Figure 9. The two gate
Disable
T
/SYNC pin. See the
FIGURE 19. Typical Feedback Network
(Continued)
CC
regulator
(1)
T
15
controlled by an external error amplifier/optocoupler feed-
back circuit to regulate the converter output voltage. Inter-
nally, the voltage at the COMP pin passes through two level
shifting diodes and a gain reducing 3:1 resistor divider (see
Figure 19). The compensated current ramp signal is a com-
bination of the current waveform at the CS pin, and an
internally generated ramp derived from the internal clock. At
duty cycles greater than 50% current mode control circuits
are prone to subharmonic oscillation. By adding a small fixed
ramp to the external current sense signal oscillations can be
avoided. The internal ramp has an amplitude of 45 µA and is
sourced into an internal 2kΩ resistor, and a 42 kΩ resistor in
parallel with the external impedance at the CS pin. The ramp
current also flows through the external impedance con-
nected to the CS pin and thus, the amount of slope compen-
sation can be adjusted by varying the external circuit at the
CS pin.
The output of the PWM comparator provides the pulse width
information to the output drivers. This comparator is opti-
mized for speed in order to achieve minimum controllable
duty cycles. The comparator’s output duty cycle is 0% for
V
If either Soft-start pin is pulled low (internally or externally)
the corresponding COMP pin is pulled down with it, forcing
the output duty cycle to zero. When the Soft-start pin voltage
increases, the COMP pin is allowed to increase. An internal
5 kΩ resistor connected from COMP to an internal 5.0V
supply provides a pull-up for the COMP pin and bias current
to the collector of the opto-coupler transistor.
COMP
≤1.5V, and increases as V
COMP
increases.
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