lm5034mtcx National Semiconductor Corporation, lm5034mtcx Datasheet - Page 22

• Manufacturer Part Number: lm5034mtcx
• Description: High Voltage Dual Interleaved Current Mode Controller With Active Clamp
• Manufacturer: National Semiconductor Corporation

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Applications Information
HICCUP MODE CURRENT LIMIT RESTART
This circuit’s operation is described in the Functional De-
scription. Also see Figure 20 and Figure 21. In the case of
continuous current limit detection at both CS pins, the time
required to reach the 2.55V RES pin threshold is:
For example, if C
approximately 12.75 ms.
In the case of continuous current limit detection at one CS
pin only, the time to reach the 2.55V threshold is increased
by a factor of four, or:
The time t2 in Figure 21 is set by the capacitor at each SS
pin and the internal 1 µA current source, and is equal to:
FIGURE 30. Current Sense Using a Current Sense
FIGURE 31. Current Sense Using a Source Sense
RES
t1 = 5.1 x 10
= 0.1 µF the time t1 in Figure 21 is
Resistor (R1)
Transformer
5
x C
RES
(Continued)
20136831
20136832
22
If C
50 µA current source, and is equal to:
The time t2 provides a periodic dwell time for the converter in
the event of a sustained overload or short circuit. This results
in lower average input current and lower power dissipated
within the circuit components. It is recommended that the
ratio of t2/(t1 + t3) be in the range of 5 to 10 to make good
use of this feature.
If the application requires no delay from the first detection of
a current limit condition, so that t1 is effectively zero, the
RES pin can be left open (no external capacitor). If it is
desired to disable the hiccup mode current limit operation
then the RES pin should be connected to ground.
SOFT-START
The capacitors at SS1 and SS2 determine the time required
for each regulator’s output duty cycle to increase from zero
to its final value for regulation. The minimum acceptable time
is dependent on the output capacitance and the response of
each feedback loop to the COMP pin. If the Soft-start time is
too quick, the output could significantly overshoot its in-
tended voltage before the feedback loop has a chance to
regulate the PWM controller.
After power is applied and V
threshold ()7.6V), the voltage at each SS pin ramps up as
its external capacitor is charged up by an internal 50 µA
current source (see Figure 3). The voltage at the COMP pins
follow the SS pins. When both have reached )1.5V, PWM
pulses appear at the driver outputs with very low duty cycle.
The voltage at each SS pin continues to increase to )5.0V.
The voltage at each COMP pin, and the PWM duty cycle,
increase to the value required for regulation as determined
by its feedback loop. The time t1 in Figure 3 is calculated
from:
With a 0.1 µF capacitor at SS, t1 is )3 ms.
If the Hiccup Mode Current Limit Restart circuit activates due
to repeated current limit detections at CS1 and/or CS2, both
SS1 and SS2 are internally grounded (see the section on
Hiccup Mode Current Limit Restart). After a short propaga-
tion delay, the SS pins are released and the external SS pin
capacitors are charged by internal 1 µA current sources. The
slow charge rate provides a rest or dwell time for the con-
verter power stage (t2 in Figure 21), reducing the average
input current and component temperature rise while in an
overload condition. When the voltage at the SS and COMP
pins reach )1.5V, the first pulse out of either PWM compara-
tor switches the internal SS pin current sources to 50 µA.
The voltages at the SS and COMP pins then increase more
quickly, increasing the duty cycle at the output drivers. The
rest time t2 is the time required for SS to reach 1.5V:
SS
= 0.1 µF t2 is )150 ms. Time t3 is set by the internal
CC
has passed its upper UVT