lm5034mtcx National Semiconductor Corporation, lm5034mtcx Datasheet - Page 3

• Manufacturer Part Number: lm5034mtcx
• Description: High Voltage Dual Interleaved Current Mode Controller With Active Clamp
• Manufacturer: National Semiconductor Corporation

Pin Description
PIN
10
11
12
13
14
15
16
17
18
19
20
6
7
8
9
RT/SYNC Oscillator Adjust and
COMP2
NAME
UVLO
GND1
GND2
VCC1
OUT1
OUT2
VCC2
RES
DCL
AC1
AC2
SS2
CS2
VIN Under-Voltage Lockout
Start-up regulator output,
Controller 1
Main Gate Driver, Controller 1
Active Clamp Driver, Controller 1
Ground, Controller 1
Ground, Controller 2
Active Clamp Driver, Controller 2
Main Gate Driver, Controller 2
Start-up regulator output,
Controller 2
Hiccup mode restart adjust
Soft-start, Controller 2
Current Sense Input, Controller 2
PWM Control, Controller 2
Duty Cycle Limit
Synchronizing input
DESCRIPTION
(Continued)
An external resistor divider sets the input voltage threshold to enable
the LM5034. The UVLO comparator reference voltage is 1.25V. A
switched 20 µA current source provides adjustable UVLO hysteresis.
The UVLO pin voltage also controls the maximum duty cycle as
described in the Functional Description section.
Output of the 7.7V high voltage start-up regulator for Controller 1. The
sum of the currents drawn from VCC1 and VCC2 should not exceed
19 mA.
Gate driver output to the primary side switch for Controller 1. OUT1
swings between VCC1 and GND1 at a frequency equal to half the
oscillator frequency.
Gate driver output to the active clamp P-channel MOSFET for
Controller 1. The AC1 pulse overlaps the leading and trailing edges of
the OUT1 pulse by an interval set by the OVLP pin resistor. The
overlap produces deadtime between the main switch transistor and the
P-channel active clamp transistor.
Ground connection for Controller 1 including gate drivers, PWM
controller, soft-start and support functions.
Ground connection for Controller 2 including gate drivers, PWM
controller and soft-start.
Gate driver output to the active clamp P-channel MOSFET for
Controller 2. The AC2 pulse overlaps the leading and trailing edges of
the OUT2 pulse by an interval set by the OVLP pin resistor. The
overlap produces deadtime between the main switch transistor and the
P-channel active clamp transistor.
Gate driver output to the primary side switch for Controller 2. OUT2
swings between VCC2 and GND2 at a frequency equal to half the
oscillator frequency.
Output of the 7.7V high voltage start-up regulator for Controller 2. The
sum of the currents drawn from VCC1 and VCC2 should not exceed
19 mA.
An external capacitor sets the time delay before forced restart during a
sustained period of cycle-by-cycle current limiting. The hiccup mode
comparator threshold is 2.55V.
An internal 50 µA current source charges an external capacitor to set
the soft-start rate. During a current limit restart sequence, the internal
current source is reduced to 1µA to increase the delay before retry.
Forcing SS2 below 0.5V shuts off Controller 2.
Input for current mode control and the current limit sensing. If the CS2
pin exceeds 0.5V the OUT2 pulse is terminated producing
cycle-by-cycle current limiting. External resistance connected to CS2
will adjust (increase) PWM slope compensation. This pin’s voltage
must not exceed 1.25V.
The COMP2 input provides voltage feedback to the PWM comparator
inverting input of Controller 2 through a 3:1 divider. The OUT2 duty
cycle increases as the COMP2 voltage increases. An internal 5kΩ
pull-up resistor to +5.0V provides bias current to the opto-coupler
transistor.
An external resistor sets the maximum allowed duty cycle at OUT1
and OUT2.
An external resistor sets the oscillator frequency. This pin also accepts
ac-coupled synchronization pulses from an external source.
3
APPLICATIONS INFORMATION
www.national.com