lm5034mtcx National Semiconductor Corporation, lm5034mtcx Datasheet - Page 18

• Manufacturer Part Number: lm5034mtcx
• Description: High Voltage Dual Interleaved Current Mode Controller With Active Clamp
• Manufacturer: National Semiconductor Corporation

www.national.com
Soft-start
Each soft-start circuit allows the corresponding regulator to
gradually reach a steady state operating point, thereby re-
ducing startup current surges and output overshoot. Upon
turn-on, both SS pins are internally held at ground. When
VCC increases past its under-voltage threshold (UVT), the
SS pins are released and internal 50 µA current sources
charge the external capacitors. The voltage at each COMP
pin follows the SS pin, and when COMP reaches )1.5V, the
output pulses commence at a low duty cycle. The voltage at
the SS pins continues to increase and saturates at )5.0V,
The voltage at each COMP pin increases to the value re-
quired for regulation where it is controlled by its voltage
feedback loop (see Figure 3).
If the internal Drivers Off line is activated (see the Drivers Off
paragraph), both SS pins are internally grounded. The SS
pins pull the COMP pins to ground while the Driver Off signal
disables the output drivers. When the event which activated
the Drivers Off line is cleared and Vcc exceeds its under-
voltage threshold, the SS pins are released. The internal 50
µA current sources then charge the external soft-start ca-
pacitors allowing each regulator’s output duty cycle to in-
crease.
If the Current Limit Restart threshold is reached due to
repeated over-current detections, both SS pins (and the
COMP pins) are pulled to ground. The output drivers are
disabled, and the 50 µA SS pin current sources are reduced
to 1 µA. After a short propagation delay the SS pins and the
COMP pins are released, and the external capacitors are
charged up at a slow rate. When the COMP voltage reaches
) 1.5V, the output drivers are enabled, and the current
sources at the SS pins are increased to 50 µA. The output
duty cycle then increases to the value required for regula-
tion.
To shutdown one regulator without affecting the other,
ground the appropriate SS pin. This forces the COMP pin to
ground, reducing the output duty cycle to zero for that regu-
lator. Releasing the SS pin allows normal operation to re-
sume.
Output Duty Cycle
The output driver’s duty cycle for each controller is normally
controlled by comparing the voltage provided to the COMP
input by the external voltage feedback circuit with the current
information at the CS pin. However, the maximum duty cycle
during transient or fault conditions may be intentionally lim-
ited by two other circuits, both of which are common to the
two controller channels.
User Defined Maximum Duty Cycle. The maximum al-
lowed duty cycle can be set with the R
from the DCL pin to GND1, according to the following equa-
tion:
R
nected to the R
must be calculated after the R
Figure 10. Referring to the block diagrams of Figure 1, and
Figure 2, the voltage at the DCL pin (V
the Ramp1 and Ramp2 signals, creating the UserMaxDC1
T
is the oscillator frequency programming resistor con-
Maximum User Duty Cycle = 80% x R
T
/SYNC pin. The value of the R
T
resistor is selected. See
DCL
DCL
resistor connected
) is compared to
DCL
DCL
/R
T
resistor
(2)
18
and UserMaxDC2 timing signals. These signal are provided
to the two 4-input AND gates to limit the PWM duty cycle of
both channels.
Line Voltage Maximum Duty Cycle. The voltage at the
UVLO pin, normally proportional to the voltage at V
further limits the maximum duty cycle at high input voltages.
Referring to Figure 11, when the UVLO pin is below 1.25V,
the outputs are disabled. At UVLO = 1.25V the maximum
allowed duty cycle is 80% (or less if limited by the DCL
resistor). As the UVLO pin voltage increases with V
maximum duty cycle decreases, reaching a minimum of 10%
at )4.5V. Referring to Figure 1 and Figure 2, the UVLO
voltage, after passing through an inverting gain stage, is
compared to the Ramp1 and Ramp2 signals generated by
the oscillator. The output of these comparators are the
MaxDC1 and MaxDC2 timing signals. These signals are
provided to the two 4-input AND gates which limit the PWM
pulses delivered to the output drivers.
Resulting Output Duty Cycle. The controller duty cycle is
determined by the four signals into the 4-input AND gates in
Figure 1 (UserMaxDC, MaxDC, PWM and CLK). The output
driver pulsewidth is equal to the least of these four pulses.
Whichever input of the AND gate transitions high-to-low first
terminates the output driver’s on-time. For example, in Fig-
ure 2, the OUT1 driver’s on-time is set by PWM Comparator
#1. The on-time for OUT2 is limited by the UVLO pin voltage
(determined by V
is seeking a higher duty cycle.
Driver Outputs
OUT1, the primary switch driver for Controller 1 is designed
to drive the gate of an N-channel MOSFET with 1.5A sourc-
ing current and 2.5A sinking current. The corresponding
active clamp driver, AC1, is designed to drive a P-channel
MOSFET and is capable of sourcing 100 mA and sinking 250
mA. The peak output levels at OUT1 and AC1 are VCC1 and
GND1. The ground return path for Controller 1 is GND1. The
corresponding driver pins for Controller 2 are OUT2, AC2,
VCC2 and GND2.
OUT1 and OUT2 are compound gate drivers with CMOS
and Bipolar output transistors as shown in Figure 22. The
parallel MOS and Bipolar devices provide a faster turn-off of
the primary switch thereby reducing switching losses. The
outputs switch at one-half the oscillator frequency with the
rising edges at OUT1 and OUT2 180˚ out of phase with each
other. The on-time of OUT1 and OUT2 is determined by their
respective duty cycle control. The active clamp outputs are
in phase with their respective main outputs, with their edge
timing altered by the overlap control circuit as shown in
Figure 23. The overlap time provides deadtime between the
operation of the primary switch and the active clamp switch
at both the rising and falling edges. The overlap times are
the same at the rising and falling edges, independent of
frequency and duty cycle. The overlap time is programmed
by the resistor at the OVLP pin (R
following equation (see Figure 13 and Figure 15):
where R
R
overlap time, the OVLP pin should be left open.
OVLP
is 10 kΩ to 100 kΩ. If the application requires zero
OVLP
is in kΩ, and t
t
PWR
OVLP
) even though the PWM Comparator #2
= (1.25 x R
OVLP
OVLP
is in ns. The range for
OVLP
) + 5
) according to the
PWR
PWR
, the
,