lm5034mtcx National Semiconductor Corporation, lm5034mtcx Datasheet - Page 23

• Manufacturer Part Number: lm5034mtcx
• Description: High Voltage Dual Interleaved Current Mode Controller With Active Clamp
• Manufacturer: National Semiconductor Corporation

Applications Information
With a 0.1 µF capacitor at SS, t2 is )150 ms.
Experimentation with the startup sequence and over-current
restart condition is usually necessary to determine the ap-
propriate value for the SS capacitors.
To shutdown one regulator without affecting the other,
ground the appropriate SS pin with an open collector or open
drain device as shown in Figure 32. The SS pin forces the
COMP pin to ground which reduces the PWM duty cycle to
zero for that regulator. Releasing the SS pin allows normal
operation to resume.
When the LM5034’s two controller channels are configured
to provide a single high current output, SS1 and SS2 are
typically connected together, requiring a single capacitor for
the two pins.
LINE VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As V
maximum allowed duty cycle decreases according to the
graph of Figure 11. Using values from the example above
(R1 = 150 kΩ, R2 = 10 kΩ in Figure 27), the maximum duty
cycle varies as shown in Figure 12. If it is desired to increase
the slope of the ramp in Figure 12, Figure 33 shows a
suggested configuration. After the LM5034 is enabled, Z1
clamps the voltage across R1B, and UVLO increases with
V
USER DEFINED MAX DUTY CYCLE
The maximum allowed duty cycle at OUT1 and OUT2 can be
set with a resistor from DCL to GND1. See Figure 10 and
Equation 2. The default maximum duty cycle (80%) deter-
mined by the internal clock signals can be selected by set-
ting R
FIGURE 33. Altering the Slope of Duty Cycle vs. V
PWR
FIGURE 32. Shutting Down One Regulator Channel
PWR
DCL
at a rate determined by the ratio R2/(R1A + R2).
= R
increases and the voltage at UVLO follows, the
T
. The oscillator frequency setting resistor (R
(Continued)
20136839
PWR
20136838
T
)
23
must be determined before R
should not be left open.
PRINTED CIRCUIT (PC) BOARD LAYOUT
The LM5034 Current Sense and PWM comparators are very
fast, and respond to short duration noise pulses. The com-
ponents at the CS, COMP, SS, DCL, UVLO, OVLP and the
RT/SYNC pins should be as physically close as possible to
the IC, thereby minimizing noise pickup in the PC board
tracks.
Layout considerations are critical for the current sense filter.
If current sense transformers are used, both leads of each
transformer secondary should be routed to the sense filter
components and to the IC pins. The ground side of each
transformer should be connected via a dedicated PC board
track to its appropriate GND pin, rather than through the
ground plane.
If the current sense circuits employ sense resistors in the
drive transistor sources, low inductance resistors should be
used. In this case, all the noise sensitive low current ground
tracks should be connected in common near the IC, and then
a single connection made to the power ground (sense resis-
tor ground point). The outputs of the LM5034 should have
short direct paths to the power MOSFETs in order to mini-
mize inductance in the PC board traces.
The two ground pins (GND1, GND2) must be connected
together with a short direct connection to avoid jitter due to
relative ground bounce in the operation of the two regulators.
If the internal dissipation of the LM5034 produces high junc-
tion temperatures during normal operation, the use of wide
PC board traces can help conduct heat away from the IC.
Judicious positioning of the PC board within the end product,
along with use of any available air flow (forced or natural
convection) can help reduce the junction temperatures.
APPLICATION CIRCUIT EXAMPLE
Figure 38 shows an example of an LM5034 controlled 200W
dual interleaved regulator which provides two independent
regulated outputs or a single high current output. The input
voltage range (V
are 3.3V and 2.5V in the dual output mode, or 3.3V in the
single output mode. The output current capability is 30A from
each output or 60A in the single output mode. Current sense
transformers T1 and T2 provide information to the CS2 and
CS1 pins for the current mode control, and error amplifiers
U3 and U4 provide voltage feedback to COMP2 and COMP1
via optocoupler U2. Synchronous rectifiers Q5-Q12 minimize
rectification losses in the secondaries. An auxiliary winding
on inductor L2 provides power to the LM5034 VCC pins
when the outputs are enabled. The UVLO levels are )34.3V
for increasing V
circuit can be shut down by forcing the ON/OFF input (J2)
below 1.25V. An external synchronizing frequency can be
applied to the SYNC input (J3). Each regulator output is
current limited at )31.5A.
To configure the circuit for two independent outputs, jumper
A-B is installed, and the other jumpers connections (C
through G) are left open. U5 and U6 are the references for
the two error amplifiers which control the LM5034’s COMP
pins via the optocouplers. See Figure 34.
To configure the circuit for a single high current output,
jumpers B-C, D-E, and F-G are installed and A-B is removed.
Output terminals J8 and J6 are connected together at the
load, as well as the ground terminals J5 and J7. In this mode
U4 is a follower to error amplifier U3, and the optocoupler
PWR
PWR
, and )32.3V for decreasing V
) is 36V to 78V, and the output voltages
DCL
is selected. The DCL pin
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PWR
. The