lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 14

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

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Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate (Q
operating conditions (t
charged by an internal 20 µA current source. The charge
pump peak voltage is roughly 13.5V, which will force a V
across Q1 of 13.5V under normal operation. When the system
voltage is initially applied, the GATE pin is held low by a 115
mA pull-down current. This helps prevent an inadvertent turn-
on of Q
system voltage increases.
During the insertion time (t
low by a 4.2 mA pull-down current. This maintains Q
off-state until the end of t
UVLO. Following the insertion time, during t
gate voltage of Q
dissipation level from exceeding the programmed levels.
While in the current or power limiting mode, the TIMER pin
capacitor is charging. If the current and power limiting cease
before the TIMER pin reaches 3.9V the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If
the in-rush limiting condition persists such that the TIMER pin
reached 3.9V during t
4.2 mA pull-down current. The GATE pin is then held low until
either a power up sequence is initiated (RETRY pin to VDD),
1
through its drain-gate capacitance as the applied
1
is modulated to keep the current or power
2
, the GATE pin is then pulled low by the
3
1
in
, regardless of the voltage at VIN or
1
Figure
in
Figure
2) the gate of Q
FIGURE 2. Power Up Sequence (Current Limit Only)
2) the GATE pin is held
1
). During normal
2
in
Figure 2
1
1
is held
in the
the
GS
14
or an automatic retry is attempted (RETRY pin to GROUND
or floating). See the Fault Timer & Restart section. If the sys-
tem input voltage falls below the UVLO threshold, or rises
above the OVLO threshold, the GATE pin is pulled low by the
4.2 mA pull-down current to switch off Q
Current Limit
The current limit threshold is reached when the voltage across
the sense resistor R
voltage limit of 26 mV or 50 mV depending on whether the CL
pin is connected to VDD or GND, respectively. In the current
limiting condition, the GATE voltage is controlled to limit the
current in MOSFET Q
the fault timer is active as described in the Fault Timer &
Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the
LM5066 resumes normal operation. If the current limit condi-
tion persists for longer than the Fault Timeout Period set by
C
the INPUT bit in the STATUS_WORD (79h) register, and
IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD
(E1h) register will be toggled high and SMBA pin will be as-
serted. SMBA toggling can be disabled using the
ALERT_MASK (D8h) register. For proper operation, the R
resistor value should be no higher than 200 mΩ. Higher val-
T
, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register,
S
1
. While the current limit circuit is active,
(VIN to SENSE) exceeds the internal
1
.
30115913
S