lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 16

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

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Under-Voltage Lockout (UVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lockout (OVLO) levels. Typically the UVLO level at
V
5. Refering to the Block Diagram when V
level, the internal 20 µA current source at UVLO is enabled,
the current source at OVLO is off, and Q
4.2 mA pull-down current at the GATE pin. As V
creased, raising the voltage at UVLO above its threshold the
20 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO/EN pin above its threshold, Q
the 20 µA current source at the GATE pin if the insertion time
delay has expired.
See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The mini-
mum possible UVLO level at V
UVLO/EN pin to VIN. In this case Q
sertion time when the voltage at VIN reaches the POR thresh-
old. After power up an UVLO condition will cause the INPUT
bit
VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register,
and
DIAGNOSTIC_WORD (E1h) registers to be toggled high and
SMBA pin will be pulled low unless this feature is disabled
using the ALERT_MASK (D8h) register.
Over-Voltage Lockout (OVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lockout (OVLO) levels. If V
voltage above its threshold, Q
pull-down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 21 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When V
below the OVLO level Q
will toggle the VIN_OV_FAULT bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h)
register and the VIN_OVERVOLTAGE_FAULT bit in the
IN
is set with a resistor divider (R1-R3) as shown in
in
the
the
VIN_UNDERVOLTAGE_FAULT
STATUS_WORD
IN
IN
) is within the operating range defined by
) is within the operating range defined by
1
is re-enabled. An OVLO condition
IN
1
1
1
) is enabled when the input
) is enabled when the input
is switched off by the 4.2 mA
can be set by connecting the
1
IN
(79h)
is enabled after the in-
raises the OVLO pin
IN
1
1
is below the UVLO
is switched on by
is held off by the
register,
bit
IN
FIGURE 4. Restart Sequence
is reduced
IN
in
Figure
is in-
the
the
16
DIAGNOSTIC_WORD (E1h) register. The SMBA pin will be
pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register.
See the Applications Section for a procedure to calculate the
threshold setting resistor values.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO/EN pin below its threshold with an open collector or
open drain device, as shown in
UVLO/EN pin the LM5066 switches on the load current with
in-rush current and power limiting.
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 80V
in the off-state, and transients up to 100V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage at the
FB pin exceeds the PGD threshold voltage. Typically the out-
put voltage threshold is set with a resistor divider from output
to feedback, although the monitored voltage need not be the
output voltage. Any other voltage can be monitored as long
as the voltage at the FB pin does not exceed its maximum
rating. Referring to the Block Diagram, when the voltage at
FIGURE 5. Shutdown Control
Figure
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5. Upon releasing the
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