lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 21

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

TIMER CAPACITOR, C
The TIMER pin capacitor (C
time delay, fault timeout period, and the restart timing of the
LM5066.
A) Insertion Delay - Upon applying the system voltage (V
to the circuit, the external MOSFET (Q
insertion time (t
V
card plug-in is unique, the worst case settling time must be
determined for each application. The insertion time starts
when VIN reaches the POR threshold, at which time the in-
ternal 4.8 µA current source charges C
required capacitor value is calculated from:
For example, if the desired insertion delay is 250 ms, C
culates to 0.3 µF. At the end of the insertion delay, C
quickly discharged by a 1.5 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q
timer current source (75 µA) is switched on to charge C
Fault Timeout Period is the time required for the TIMER pin
voltage to reach 3.9V, at which time Q
required capacitor value for the desired Fault Timeout Period
t
For example, if the desired Fault Timeout Period is 15 ms,
C
sink at the end of the Fault Timeout Period. After the Fault
Timeout Period, if retry is disabled, the LM5066 latches the
GATE pin low until a power up sequence is initiated by exter-
nal circuitry. When the Fault Timeout Period of the LM5066
FAULT
IN
T
calculates to 0.3 µF. C
to settle. Since each backplane’s response to a circuit
is calculated from:
1
in
Figure
T
T
2) to allow ringing and transients at
is discharged by the 2.5 µA current
T
) sets the timing for the insertion
1
T
) is held off during the
1
from 0V to 3.9V. The
is switched off. The
FIGURE 9. MOSFET Power Up Waveforms
1
, the fault
T
T
. The
cal-
T
(7)
(8)
IN
is
)
21
expires, a restart sequence starts as described below
(Restart Timing). During consecutive cycles of the restart se-
quence, the fault timeout period is shorter than the initial fault
time out period described above by approximately 8% since
the voltage at the TIMER pin starts ramping up from 0.3V
rather than ground.
Since the LM5066 normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-On Time section.
C) Restart Timing For the LM5066, after the Fault Timeout
Period described above, C
rent sink to 1.1V. The TIMER pin then cycles through seven
additional charge/discharge cycles between 1.1V and 3.9V as
shown in
voltage reaches 0.3V during the final high-to-low ramp. The
restart time, after the Fault Timeout Period, is equal to:
For example, if C
end of the restart time, Q
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM5066 enables the series pass device (Q
supply voltage (V
V
old, Q
is provided for each threshold.
Option A: The configuration shown in
three resistors (R1-R3) to set the thresholds.
IN
is below the UVLO threshold, or above the OVLO thresh-
1
is switched off, denying power to the load. Hysteresis
Figure
4. The restart time ends when the TIMER pin
IN
T
) is within the desired operational range. If
= 0.8 µF, t
= C
1
T
T
is switched on. If the fault is still
is discharged by the 2.5 µA cur-
x 9.5 x 10
RESTART
= 7.9 seconds. At the
6
Figure 10
1
) when the input
www.national.com
30115925
requires
(10)
(9)