lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 15

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

ues may create instability in the current limit control loop. The
current limit threshold pin value may be overridden by setting
appropriate bits in the DEVICE_SETUP register (D9h).
Circuit Breaker
If the load current increases rapidly (e.g., the load is short
circuited) the current in the sense resistor (R
the current limit threshold before the current limit control loop
is able to respond. If the current exceeds 1.94x or 3.87x (CL
= GND) the current limit threshold, Q
by the 115 mA pull-down current at the GATE pin, and a Fault
Timeout Period begins. When the voltage across R
low the circuit breaker (CB) threshold, the 115 mA pull-down
current at the GATE pin is switched off, and the gate voltage
of Q
functions. If the TIMER pin reaches 3.9V before the current
limiting or power limiting condition ceases, Q
by the 4.2 mA pull-down current at the GATE pin as described
in the Fault Timer & Restart section. A circuit breaker event
will cause the CIRCUIT BREAKER FAULT bit in the
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD
(E1h) registers to be toggled high and SMBA pin will be as-
serted unless this feature is disabled using the ALERT_MASK
(D8h) register. The circuit breaker pin configuration may be
overridden by setting appropriate bits in the DEVICE_SETUP
(D9h) register.
Power Limit
An important feature of the LM5066 is the MOSFET power
limiting. The Power Limit function can be used to maintain the
maximum power dissipation of MOSFET Q
SOA rating. The LM5066 determines the power dissipation in
Q
and the drain current through the R
product of the current and voltage is compared to the power
limit threshold programmed by the resistor at the PWR pin. If
the power dissipation reaches the limiting threshold, the
GATE voltage is modulated to regulate the current in Q
While the power limiting circuit is active, the fault timer is ac-
tive as described in the Fault Timer & Restart section. If the
power limit condition persists for longer than the Fault Time-
out Period set by the timer capacitor, C
in the STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD
PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will be toggled high and SMBA pin will be asserted
unless this feature is disabled using the ALERT_MASK (D8h)
register.
1
by monitoring its drain-source voltage (SENSE to OUT),
1
is then determined by the current limit or the power limit
(79h)
register,
S
1
is quickly switched off
(VIN to SENSE). The
T
and
, the IIN OC Fault bit
1
within the device
1
S
is switched off
the
) may exceed
S
IIN_OC/
falls be-
1
.
15
Fault Timer & Restart
When the current limit or power limit threshold is reached
during turn-on, or as a result of a fault condition, the gate-to-
source voltage of Q
and power dissipation in Q
active, a 75 µA fault timer current source charges the external
capacitor (C
Timeout Period). If the fault condition subsides during the
Fault Timeout Period before the TIMER pin reaches 3.9V, the
LM5066 returns to the normal operating mode and C
charged by the 1.5 mA current sink. If the TIMER pin reaches
3.9V during the Fault Timeout Period, Q
4.2 mA pull-down current at the GATE pin. The subsequent
restart procedure then depends on the selected retry config-
uration.
If the RETRY pin is high, the LM5066 latches the GATE pin
low at the end of the Fault Timeout Period. C
charged to ground by the 2.5 µA fault current sink. The GATE
pin is held low by the 4.2 mA pull-down current until a power
up sequence is externally initiated by cycling the input voltage
(V
threshold with an open-collector or open-drain device as
shown in
<0.3V for the restart procedure to be effective. The
TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD
(E1h) register will remain high while the latched off condition
persists.
The LM5066 provides an automatic restart sequence which
consists of the TIMER pin cycling between 3.9V and 1.1V
seven times after the Fault Timeout Period, as shown in
ure
charging current, and the 2.5 µA discharge current, and the
value of the capacitor C
during the eighth high-to-low ramp, the 20 µA current source
at the GATE pin turns on Q
present, the Fault Timeout Period and the restart sequence
repeat. The RETRY pin allows selecting no retries or infinite
retries. Finer control of the retry behavior can be achieved
through the DEVICE_SETUP (D9h) register. Retry counts of
0, 1, 2, 4, 8, 16 or infinite may be selected by setting the ap-
propriate bits in the DEVICE_SETUP (D9h) register.
IN
), or momentarily pulling the UVLO/EN pin below its
4. The period of each cycle is determined by the 75 µA
FIGURE 3. Latched Fault Restart Control
Figure
T
) at the TIMER pin as shown in
3. The voltage at the TIMER pin must be
1
is modulated to regulate the load current
T
. When the TIMER pin reaches 0.3V
1
. When either limiting function is
1
. If the fault condition is still
1
is switched off by a
Figure 2
T
www.national.com
is then dis-
T
(Fault
is dis-
Fig-
30115915