lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 34

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

www.national.com
MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
The MFR_PIN_OP_WARN_LIMIT PMBus command sets the
input over-power warning threshold. In the event that the input
power rises above the value set in this register, the PIN Over-
power flags are set in the respective registers and the SM-
BA is asserted. To access the MFR_PIN_OP_WARN_LIMIT
register, use the PMBus Read/Write Word protocol. Reading/
writing to this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table.
MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
The READ_PIN_PEAK command will report the maximum
input power measured since a Power On reset or the last
CLEAR_PIN_PEAK
READ_PIN_PEAK command, use the PMBus Read Word
protocol. Use the coefficients shown in the Telemetry and
Warning Coefficients Table.
MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
The CLEAR_PIN_PEAK command will clear the PIN PEAK
register. This command uses the PMBus Send Byte protocol.
Value
0h – 0FFEh
0FFFh
Value
0h – 0FFEh
0FFFh
Value
0h – 0FFEh
TABLE 25. MFR_IIN_OC_WARN_LIMIT Register
TABLE 26. MFR_PIN_OPWARN_LIMIT Register
TABLE 27. READ_PIN_PEAK Register
BIT
15
14
13
12
11
10
Meaning
Value for input
over-current warn
limit
Input over-current
warning disabled
Meaning
Value for input
over power warn
limit
Input over power
warning disabled
Meaning
Maximum Value
for input current x
input voltage since
reset or last clear
9
8
7
6
command.
To
Default
0FFFh
n/a
Default
0FFFh
n/a
Default
0h
TABLE 29. ALERT_MASK Definitions
access
VOUT UNDERVOLTAGE WARN
VIN UNDERVOLTAGE WARN
VIN OVERVOLTAGE WARN
OVERPOWER LIMIT WARN
EXT_MOSFET_SHORTED
OVERTEMP WARN
POWER GOOD
IIN LIMIT Warn
the
Not Used
Not Used
NAME
34
MFR_SPECIFIC_07: GATE_MASK (D7h)
The GATE_MASK register allows the hardware to prevent
fault conditions from switching off the MOSFET. When the bit
is high, the corresponding FAULT has no control over the
MOSFET gate. All status registers will still be updated (STA-
TUS, DIAGNOSTIC) and an SMBA will still be asserted. This
register is accessed with the PMBus Read / Write Byte pro-
tocol.
Warning: Inhibiting the MOSFET switch off in response to over-cur-
The IIN/PFET Fault refers to the input current fault and the
MOSFET power dissipation fault. There is no input power fault
detection; only input power warning detection.
MFR_SPECIFIC_08: ALERT_MASK (D8h)
The ALERT_MASK command is used to mask the SMBA
when a specific fault or warning has occurred. Each bit cor-
responds to one of the 14 different analog and digital faults or
warnings that would normally result in an SMBA being as-
serted. When the corresponding bit is high, that condition will
not cause the SMBA to be asserted. If that condition occurs,
the registers where that condition is captured will still be up-
dated (STATUS registers, DIAGNOSTIC_WORD) and the
external
(VIN_OV_FAULT,
CB_FAULT, OT_FAULT). This register is accessed with the
PMBus Read / Write Word protocol. The VIN UNDERVOLT-
AGE FAULT flag will default to 1 on startup, however, it will
be cleared to 0 after the first time the input voltage increases
above the resistor-programmed UVLO threshold.
TABLE 28. MFR_SPECIFIC_07 GATE MASK Definitions
Bit
7
6
5
4
3
2
1
0
rent or circuit breaker fault conditions will likely result in
the destruction of the MOSFET! This functionality should
be used with great care and supervision!
MOSFET
CIRCUIT BREAKER
OVERTEMP FAULT
Not used, always 0
Not used, always 0
Not used, always 0
IIN/PFET FAULT
VIN UV FAULT
VIN OV FAULT
VIN_UV_FAULT,
gate
FAULT
NAME
control
DEFAULT
will
0
0
0
0
1
0
0
0
0
0
IIN/PFET_FAULT,
still
Default
be
0
0
0
0
0
0
0
0
active