hip4020 Intersil Corporation, hip4020 Datasheet - Page 5

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hip4020

Manufacturer Part Number
hip4020
Description
Full Bridge Driver With Integrated 0.5a Power Fets For Small 3v, 5v And 12v Dc Motors
Manufacturer
Intersil Corporation
Datasheet

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Application
The HIP4020 is designed to detect load current feedback
from sampling resistors of low value in the source
connections of the output drivers to V
(See Figure 1). When the sink or source current at OUTA or
OUTB exceeds the preset OC (Overcurrent) limiting value of
550mA typical, the current is held at the limiting value. If the
OT (Over-Temperature) Shutdown Protection limit is
exceeded, temperature sensing BiMOS circuits limit the
junction temperature to 150°C typical.
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
A1 A2 ENA
H
H
X
L
L
X = Don’t Care
Z = High Impedance (off state)
L = Low logic level; H = High logic level
INPUTS
DIRECTION
SWITCH DRIVER A
H
H
X
L
L
ENABLE
BRAKE
FIGURE 1. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
OFF
H
H
H
H
L
OUTPUT
ON
OUTA
OH
OL
OL
OL
Z
TRUTH TABLE
ENB
ENA
B1
B2
A1
A2
5
B1 B2 ENB
H
H
L
L
X
INPUTS
SWITCH DRIVER B
H
H
X
L
L
DD
, V
CONTROL
H
H
H
H
CONTROL
L
LOGIC B
LOGIC A
SSA
and V
OUTPUT
OUTB
OH
OL
OL
OL
Z
SSB
V
GROUND)
SS
(LOGIC
HIP4020
FIGURE 2.
V
Q2
Q1
SSA
The circuit of Figure 1 shows the Full H-Switch in a small motor-
drive application. The left (A) and right (B) H-Switch’s are
controlled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply
current. The stop function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
OUTA
D2
D1
V
V
OUT
OUT
V
V
EN
EN
LOAD
SWITCHING WAVEFORMS
D3
OUTB
t
D4
PLH
10%
10%
50%
t
PHL
V
V
t
Q3
Q4
r
DD
SSB
50%
t
f
90%
90%
V-
V+
50%
50%
ILF
December 20, 2005
FN3976.3

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