p80cl580 NXP Semiconductors, p80cl580 Datasheet
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p80cl580 Summary of contents
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... DATA SHEET P80CL580; P83CL580 Low voltage 8-bit microcontrollers with UART, I Product specification Supersedes data of 1996 Oct 04 File under Integrated circuits, IC20 INTEGRATED CIRCUITS 2 C-bus and ADC 1997 Mar 14 ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 2.1 ROMless version: P80CL580 3 APPLICATIONS 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 FUNCTIONAL DIAGRAM 7 PINNING INFORMATION 7.1 Pinning 7.2 Pin description 8 FUNCTIONAL DESCRIPTION OVERVIEW 8.1 General 8.2 CPU timing 9 MEMORY ORGANIZATION 9.1 Program Memory 9.2 Data Memory 9 ...
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... ROMless version: P80CL580 The P80CL580 is the ROMless version of the P83CL580. The mask options on the P80CL580 are fixed as follows: All ports have option ‘1S’ (standard port, HIGH after reset), except ports P1.6 and P1.7 which have option ‘2S’ (open-drain, HIGH after reset) Oscillator option: Oscillator 3 Power-on-reset option: off ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 5 BLOCK DIAGRAM 1997 Mar 14 P80CL580; P83CL580 4 Product specification ...
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... Mar 14 EA PSEN ALE PWM0 V SSA P80CL580 ADC3 P83CL580 ADC2 ADC1 ADC0 V RST V EWN MBB541 Fig.2 Functional diagram. 5 P80CL580; P83CL580 LOW ORDER ADDRESS PORT 0 AND DATA BUS T2 INT2 T2EX INT3 STADC INT4 INT5 PORT 1 INT6 INT7 SCL INT8 SDA HIGH ORDER ...
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... P1.0/INT2/T2 P1.1/INT3/T2EX P1.2/INT4/STADC 38 P1.3/INT5 19 37 P1.4/INT6 20 P1.5/INT7 21 36 P1.6/INT8/SCL 22 35 P1.7/SDA PWM0 EWN 26 XTAL2 31 XTAL1 MBB542 Fig.3 Pin configuration for VSO56 package. 6 Product specification P80CL580; P83CL580 V DD P2.0 P2.1 P2.2 PSEN ALE EA P2.3 P2.4 P2.5 P2.6 P2.7 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TXD P3.0/RXD ...
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... P4 n.c. P4.2 4 P4.3 5 P4 P4.6 9 n.c. 10 P4.7 11 RST 12 P1.0/INT2/T2 13 P1.1/INT3/T2EX 14 P1.2/INT4/STADC 15 P1.3/INT5 P1.4/INT6 16 n.c. 17 n.c. 18 P1.5/INT7 19 1997 Mar 14 P80CL580 P83CL580 Fig.4 Pin configuration for QFP64 package. 7 Product specification P80CL580; P83CL580 n.c. 49 P2.3 48 P2.4 47 P2.5 46 P2.6 45 P2.7 44 P0.7 43 P0.6 42 P0.5 41 P0.4 40 P0.3 39 P0.2 38 P0.1 37 P0.0 36 n.c. 35 n.c. 34 P3.7/RD 33 P3.6/WR MGC765 ...
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... TXD is the UART serial data output (asynchronous) or clock output 32 (synchronous) 33 – INT0 and INT1 are external interrupts 0 and 1 34 – T0 and T1 are external inputs for timers 0 and 1. 8 Product specification P80CL580; P83CL580 DESCRIPTION , see Chapter 23) due to the internal IL 2 C-bus clock and data lines. ...
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... Memory. When executing code out of external Program Memory, PSEN is activated twice each machine cycle. However, during each access to external Data Memory two PSEN activations are skipped. 57 Power supply 17, 18, Not connected. 35, 36, 50 and 58 9 Product specification P80CL580; P83CL580 DESCRIPTION ...
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... A/D converter, Watchdog Timer and Pulse Width Modulation output. 1997 Mar 14 P80CL580; P83CL580 The device has two software-selectable modes of reduced activity for power reduction: Idle mode; freezes the CPU while allowing the derivative functions (timers, serial I/O, ADC, PWM) and interrupt system to continue functioning. Power-down mode ...
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... I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 directly addressable locations in the SFR address space. Bit addressable SFRs are those that end in 000B. 1997 Mar 14 P80CL580; P83CL580 9.4 Addressing The P8xCL580 has five methods for addressing source operands: Register ...
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... Boolean variables to provide excellent bit handling. OVERLAPPED SPACE 255 EXTERNAL INTERNAL DATA RAM ( (1) 127 (2) 0 INTERNAL DATA MEMORY Fig.6 Memory map. 12 Product specification P80CL580; P83CL580 64 kbytes SPECIAL FUNCTION REGISTERS (3) 0 EXTERNAL DATA MEMORY MGD676 ...
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... P80CL580; P83CL580 DIRECT BYTE FFH FEH FDH FCH F8 F8H F0H F0 EFH EEH EDH ECH EBH EAH E9H E8 E8H E0 E0H SFRs containing DBH directly addressable DAH ...
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... P80CL580; P83CL580 BYTE B8H B0H AFH AEH ADH ACH ABH AAH A9H A8H A0H SFRs containing directly addressable 99H bits 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H ...
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... These options are also shown in Fig.9. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up ‘p1’ is turned on for two oscillator periods after a 1997 Mar 14 P80CL580; P83CL580 LOW-to-HIGH transition in the port latch; Fig.9(a). Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor ...
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... Q from port latch 1997 Mar 14 strong pull-up 2 oscillator periods p1 n INPUT BUFFER (a) Standard n INPUT BUFFER (b) Open-drain strong pull- (c) Push-pull Fig.9 Port configuration options. 16 Product specification P80CL580; P83CL580 + I/O pin +5 V external pull-up I/O pin I/O pin MGD677 ...
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... T2EX will also trigger the 16-bit reload and set the EXF2 bit. 11.2.3 The Baud Rate Generator mode is selected when RTCLK = 1. It will be described in conjunction with the serial port (UART); see Section 16.3.2. 17 Product specification P80CL580; P83CL580 C APTURE MODE A - UTO RELOAD MODE B ...
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... EXEN2 Fig.10 Timer 2 in Capture mode control TR2 reload transition detector control EXEN2 Fig.11 Timer 2 in Auto-Reload mode. 18 P80CL580; P83CL580 TL2 TH2 TF2 (8 BITS) (8 BITS) RCAP2L RCAP2H EXF2 TL2 TH2 TF2 (8 BITS) (8 BITS) RCAP2L RCAP2H EXF2 Product specification ...
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... RTCLK CP/RL2 1997 Mar GF2 RTCLK EXEN2 C/ selects the external event counter; negative edge 12 osc TR2 1 16-bit Auto-reload 1 16-bit Capture 1 Baud Rate Generator 0 Off 19 Product specification P80CL580; P83CL580 2 1 TR2 C/T2 DESCRIPTION MODE 0 CP/RL2 ...
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... INTERNAL BUS PRESCALER TIMER T3 (8-BIT) 11-BIT LOAD CLEAR CLEAR WLE PCON.4 INTERNAL BUS Fig.12 Functional diagram of the T3 Watchdog Timer. 20 P80CL580; P83CL580 = 12 MHz. overflow LOADEN internal reset PD LOADEN PCON.1 Product specification RST R RST MGD678 ...
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... The PWM0 output pin is driven by push-pull drivers and is not shared with any other function PWMP.5 PWMP.4 PWMP.3 Prescaler division factor = (PWMP PWM0.5 PWM0.4 PWM0.3 LOW/HIGH ratio of PWM0 signal 21 P80CL580; P83CL580 ) at the PWM0 output is PWM f osc = ---------------------------------------------------------------------------- PWMP 255 = 12 MHz the above formula gives a repetition osc 3 ...
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... Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC handbook, full pagewidth osc 1/2 S MGC750 Fig.13 Functional diagram of Pulse Width Modulated output (PWM0). 1997 Mar 14 PWM0 8-BIT COMPARATOR 8-BIT COUNTER PRESCALER PWMP 22 Product specification P80CL580; P83CL580 OUTPUT PWM0 BUFFER ...
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... For the three cases mentioned above the internal flag ADCI is set upon completion of the conversion. (succesive approximation) START END INTERNAL BUS Fig.14 Functional diagram of analog input. 23 P80CL580; P83CL580 ADEX V 8-BIT ADC V SSA ADCH Product specification ...
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... Intermediate status for a maximum of one machine cycle before conversion is completed (ADCI = 1, ADCS = 0). 1997 Mar ADEX ADCI ADCS Table 12 Selection of analog input channel AADR1 AADR0 P80CL580; P83CL580 CKDIV AADR1 DESCRIPTION SELECTED CHANNEL 0 AD0 1 AD1 0 AD2 1 AD3 Product specification ...
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... Reset redefines all SFRs but does not affect the on-chip RAM. 1997 Mar 14 P80CL580; P83CL580 14.2 Power-down mode Operation in Power-down mode freezes the oscillator. The internal connections which link both Idle and Power-down signals to the clock generation circuit are shown in Fig ...
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... HIGH port data 0 0 HIGH floating 5 4 WLE 26 P80CL580; P83CL580 PORT 1 PORT 2 port data port data port data address port data port data port data port data GF1 GF0 PD DESCRIPTION Product specification ...
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... Fig.15 Internal clock control in Idle and Power-down modes. handbook, full pagewidth power-down RST pin external interrupt oscillator 1997 Mar 14 XTAL1 OSCILLATOR CLOCK GENERATOR P80CL580 P83CL580 PD delay counter 1536 periods Fig.16 Wake-up operation. 27 Product specification P80CL580; P83CL580 interrupts serial ports timer blocks CPU IDL MGL102 MGD679 24 periods ...
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... Figure 17 is the block diagram of the I 7 SLAVE ADDRESS S1ADR 7 SHIFT REGISTER S1DAT SYNC LOGIC BUS CLOCK GENERATOR 7 CONTROL REGISTER S1CON 7 STATUS REGISTER S1STA 2 Fig.17 Block diagram of I C-bus serial I/O. 28 Product specification P80CL580; P83CL580 2 C-bus serial I/ MLB199 ...
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... A Stop or Start condition is received as selected slave receiver or transmitter. Own slave address is received General call address is received; GC (S1ADR. data byte is received while the device is programmed Master Receiver A data byte is received while the device is a selected Slave Receiver. 29 P80CL580; P83CL580 ...
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... CR0 f DIVISOR osc 0 256 1 224 0 192 1 160 0 960 1 120 not allowed SC2 SC1 DESCRIPTION 30 P80CL580; P83CL580 BIT RATE(kHz 3.58 MHz 6 MHz 14.0 23.4 16.0 26.8 18.6 31.3 22.4 37.5 3.73 6.25 29.8 50.0 59.7 100.0 C-bus. The status codes for all possible modes of the SC0 0 0 DESCRIPTION Product specification osc 12 MHz 46 ...
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... Last DATA byte has been transmitted (AA = 0), ACK received. Table 25 Miscellaneous. S1STA VALUE 00H Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition. F8H No relevant state information available 1997 Mar 14 P80CL580; P83CL580 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 31 Product specification ...
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... S1DAT.5 S1DAT.4 S1DAT SLA4 SLA3 This bit is used to determine whether the general call address is recognized. When the general call address is not recognized; when the general call address is recognized. 32 P80CL580; P83CL580 3 2 S1DAT.2 S1DAT SLA2 SLA1 SLA0 DESCRIPTION Product specifi ...
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... SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. th data bit, and a stop bit th data bit (TB8 osc th data bit and a 33 Product specification P80CL580; P83CL580 Multiprocessor communications th bit goes into RB8. The following bit is the stop bit. th bit is HIGH in an ...
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... In Mode 1, if SM2 = 0 then RB8 is the stop MODE DESCRIPTION Mode 0 Shift register Mode 1 8-bit UART Mode 2 9-bit UART Mode 3 9-bit UART 34 P80CL580; P83CL580 RB8 TI DESCRIPTION th data bit (RB8 logic 0. th bit time in Mode bit time in Mode 0, or ...
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... Timer 1. f (MHz) SMOD osc (2) 12.000 X 12.000 1 12.000 1 11.059 1 11.059 0 11.059 0 11.059 0 11.059 0 11.986 0 6.000 0 12.000 0 35 P80CL580; P83CL580 SMOD 2 Timer 1 Overflow Rate. = ---------------- - 32 SMOD f 2 osc = ---------------- - ------------------------------------------------------- - 32 12 256 TH1 – C/T TIMER 1 MODE Mode 2 0 Mode 2 0 ...
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... Timer 2 or RCAP2H/RCAP2L osc should first be turned off by clearing the TR2 bit. TL2 (8 BITS) control TR2 RCAP2L EXF2 control EXEN2 Fig.18 Timer 2 in Baud Rate Generator mode. 36 P80CL580; P83CL580 TIMER 1 overflow SMOD 1 0 TH2 (8 BITS) RTCLK 16 RELOAD UART receive/ ...
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... R1 RX CLOCK RX CONTROL START INPUT SHIFT REGISTER LOAD SBUF S0 BUFFER READ SBUF INTERNAL BUS Fig.19 Serial port Mode 0. 37 P80CL580; P83CL580 RXD P3.0 ALT output function SHIFT SHIFT SEND SHIFT CLOCK RECEIVE SHIFT RXD P3.0 ALT input function ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 38 Product specification pagewidth full handbook, ...
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... ZERO DETECTOR START TX CONTROL 16 TX CLOCK serial port interrupt 16 sample RX CLOCK TRANSITION RX CONTROL START DETECTOR BIT DETECTOR Fig.21 Serial port Mode 1. 39 P80CL580; P83CL580 SHIFT SHIFT DATA SEND T1 R1 LOAD SBUF SHIFT INPUT SHIFT REGISTER (9-BITS) SHIFT LOAD SBUF S0 BUFFER READ ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 40 Product specification pagewidth full handbook, ...
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... RX CLOCK R1 RX CONTROL START BIT DETECTOR LOAD SBUF READ SBUF INTERNAL BUS Fig.23 Serial port Mode 2. 41 Product specification P80CL580; P83CL580 SHIFT SHIFT DATA SEND LOAD SBUF SHIFT INPUT SHIFT REGISTER (9-BITS) SHIFT S0 BUFFER MGC754 TXD ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 42 Product specification pagewidth full handbook, ...
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... START TX CONTROL 16 TX CLOCK serial port interrupt 16 sample RX CLOCK HIGH-TO-LOW TRANSITION RX CONTROL START DETECTOR BIT DETECTOR Fig.25 Serial port Mode 3. 43 P80CL580; P83CL580 S0 BUFFER SHIFT SHIFT DATA SEND T1 R1 LOAD SBUF SHIFT INPUT SHIFT REGISTER (9-BITS) SHIFT LOAD SBUF S0 BUFFER ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 44 Product specification pagewidth full handbook, ...
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... The interrupt request is not serviced until the next machine cycle. Figure 28 shows the external interrupt system. 1997 Mar 14 P80CL580; P83CL580 17.2 Interrupt priority Each interrupt source can be set to either a high priority low priority low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first ...
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... Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC INTERRUPT handbook, full pagewidth SOURCES ADC 1997 Mar 14 IEN0/1 IP0/1 REGISTERS GLOBAL ENABLE Fig.27 Interrupt system. 46 Product specification P80CL580; P83CL580 PRIORITY HIGH LOW MGD623 ...
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... Interrupt Priority Register F8H IP1 Interrupt Priority Register (INT2 to INT8, ADC) E9H IX1 Interrupt Polarity Register C0H IRQ1 Interrupt Request Flag Register 1997 Mar 14 IX1 IEN1 Fig.28 External interrupt configuration. DESCRIPTION 47 Product specification P80CL580; P83CL580 IRQ1 WAKE-UP ...
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... EX3 enable external interrupt 3 0 EX2 enable external interrupt 2 1997 Mar 14 (IEN0 ES1 ES0 ET1 2 C interrupt (IEN1 EX7 EX6 EX5 48 Product specification P80CL580; P83CL580 2 1 EX1 ET0 DESCRIPTION 2 1 EX4 EX3 DESCRIPTION 0 EX0 0 EX2 ...
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... PX3 external interrupt 3 priority level 0 PX2 external interrupt 2 priority level 1997 Mar 14 (IP0 PS1 PS0 2 C interrupt priority level (IP1 PX7 PX6 49 P80CL580; P83CL580 PT1 PX1 PT0 DESCRIPTION PX5 PX4 PX3 DESCRIPTION Product specification 0 PX0 0 PX2 ...
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... IQ3 external interrupt 3 request flag 0 IQ2 external interrupt 2 request flag 1997 Mar 14 (IX1) EGISTER 5 4 IL7 IL6 R (IRQ1) EGISTER 5 4 IQ7 IQ6 50 P80CL580; P83CL580 IL5 IL4 IL3 DESCRIPTION IQ5 IQ4 IQ3 DESCRIPTION Product specification 0 IL2 0 IQ2 ...
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... Table 48 and shown in Fig.29. The required option should be stated when ordering. APPLICATION QUARTZ OSCILLATOR WITH EXTERNAL CAPACITORS XTAL2 XTAL1 XTAL2 ( OSCILLATOR XTAL1 XTAL2 XTAL1 (e) Fig.29 Oscillator configurations. 51 P80CL580; P83CL580 32 kHz OSCILLATOR XTAL1 XTAL2 (c) EXTERNAL CLOCK RC - OSCILLATOR XTAL2 XTAL1 n.c. n.c. (f) Product specification XTAL2 V DD (g) ...
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... P80CL580 P83CL580 bias XTAL1 Fig.30 Standard oscillator. 600 f osc (kHz) 400 200 500 kHz. osc Fig.31 RC oscillator; frequency as a function of RC. 52 P80CL580; P83CL580 to internal timing circuits MGC756 XTAL2 MLA579 Product specification ...
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... Oscillator Oscillator Oscillator Oscillator Oscillator Product specification P80CL580; P83CL580 C2 EXT. (pF) RESONATOR MAX. SERIES RESISTANCE MIN. MAX note 600 0 15 100 ...
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... Oscillator 3 Oscillator 4 Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 54 Product specification P80CL580; P83CL580 XTAL2 C2 i MLA578 MIN. TYP. MAX. 15 200 600 1000 400 1 500 4000 1000 4000 10000 3 ...
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... The Power-on-reset circuitry is shown in Fig.34 handbook, halfpage RESET CIRCUITRY POR MGC757 Fig.34 Recommended Power-on-reset circuitry. 55 Product specification P80CL580; P83CL580 via capacitor. At power-on, the voltage minus the capacitor voltage the capacitor charges through ground. The larger the RST decreases. V RST ...
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... Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC handbook, full pagewidth SUPPLY VOLTAGE POWER-ON-RESET (INTERNAL) OSCILLATOR CPU RUNNING 1997 Mar 14 switching level POR Start-up 1536 oscillator time periods delay Fig.35 Power-on-reset switching level. 56 Product specification P80CL580; P83CL580 hysteresis MLA581 ...
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... Timer 2 Low byte 00000000 Timer 2 Reload/Capture Register High byte 00000000 Timer 2 Reload/Capture Register Low byte 00000000 Timer/Counter 2 Control Register 11111111 ADC Result Register X0000000 ADC Control Register (2) XXXXXXXX Digital I/O Port Register 4 00000000 Interrupt Request Flag Register 57 Product specification P80CL580; P83CL580 FUNCTION ...
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... Timer 0 and 1 Mode Control Register 00000000 Timer 0 and 1 Control/External Interrupt Control Register 0XX00000 Power Control Register 00000000 Data Pointer High byte 00000000 Data Pointer Low byte 00000111 Stack Pointer (2) XXXXXXXX Digital I/O Port Register 0 58 Product specification P80CL580; P83CL580 FUNCTION ...
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... Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment data pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A 1997 Mar 14 DESCRIPTION 59 Product specification P80CL580; P83CL580 OPCODE BYTES CYCLES (HEX 26 ...
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... Rotate A left RLC A Rotate A left through the carry fl Rotate A right RRC A Rotate A right through the carry flag SWAP A Swap nibbles within A 1997 Mar 14 DESCRIPTION 60 Product specification P80CL580; P83CL580 OPCODE BYTES CYCLES (HEX 56 ...
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... Exchange register with A XCH A,direct Exchange direct byte with A XCH A,@Ri Exchange indirect RAM with A XCHD A,@Ri Exchange LOW-order digit indirect RAM with A Note 1. MOV A,ACC is not permitted. 1997 Mar 14 DESCRIPTION 61 Product specification P80CL580; P83CL580 OPCODE BYTES CYCLES (HEX E6 ...
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... Compare immediate to indirect and jump if not equal DJNZ Rr,rel Decrement register and jump if not zero DJNZ direct,rel Decrement direct and jump if not zero NOP No operation 1997 Mar 14 DESCRIPTION 62 Product specification P80CL580; P83CL580 OPCODE BYTES CYCLES (HEX ...
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... Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is 128 to +127 bytes relative to first byte of the following instruction. Hexadecimal opcode cross-reference * 1997 Mar 14 P80CL580; P83CL580 DESCRIPTION 63 Product specification ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 64 Product specification ...
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... P80CL580; P83CL580 MIN. 0.5 0.5 5.0 5 MIN. TYP. 2.5 1 MHz; note 3 = 3.58 MHz; note MHz; note 4 = 3.58 MHz; note note 0. 0.4 V 1.6 = 0.4 V 0.7 = 0.4 V 3.0 = 0.4 V 3 ...
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... 0. 2 SSA ref(p)(A) DD amb 66 P80CL580; P83CL580 MIN. TYP SSA 2 100 pF), the noise pulse C-bus specification. Therefore, an input voltage will be recognized as a logic +85 C, unless otherwise specified. ...
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... Oscillator option = Oscillator 3. Fig.37 Typical operating current as a function of MGC763 handbook, halfpage I DD(pd MHz 8.0 MHz 3.58 MHz ( amb Fig.39 Typical Power-down current as a function of 67 Product specification P80CL580; P83CL580 MHz 12 8.0 MHz 6 3.58 MHz frequency and ...
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... The ideal transfer curve. (3) Differential non-linearity ( (4) Absolute error. 1997 Mar 14 (2) (3) 1 LSB (ideal 250 251 252 253 254 255 Fig.40 Analog-to-digital conversion characteristics. 68 Product specification P80CL580; P83CL580 (4) (1) V IN(A) (LSB ideal ) MGD625 V – V ref p (A) SSA 1LSB = ------------------------------------------ - 256 ...
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... Product specification P80CL580; P83CL580 = 40 pF for all other outputs VARIABLE osc UNIT MIN. MAX CLK CLK CLK 4t 100 ns CLK ...
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... LLDV t LLWL t LLAX t t RLDV AVWL RLAZ t AVDV address A8 to A15 (DPH) or Port 2 Fig.42 Read from Data Memory. 70 Product specification P80CL580; P83CL580 t PXIZ inst. input t PXIX address A8 to A15 t WHLH t RLRH t RHDZ t RHDX data input MGD680 MGA177 ...
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... C-bus and ADC handbook, full pagewidth t LHLL ALE PSEN WR t AVLL PORT 0 PORT 2 1997 Mar LLWL t AVWL t LLAX t QVWX address A8 to A15 (DPH) or Port 2 Fig.43 Write to Data Memory. 71 Product specification P80CL580; P83CL580 t WHLH t WLWH t QVWH t WHQX data output MGA178 ...
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... address A8 - A15 address A8 - A15 or Port 2 output old data old data sampling time of I/O port pins during input Fig.44 Instruction cycle timing. 72 Product specification P80CL580; P83CL580 one machine cycle inst. address inst ...
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... Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC handbook, halfpage handbook, 4 columns 500 A 100 A 1997 Mar test points 0 0 Fig.45 AC testing input waveform. I IL( 0 Fig.46 Input current. 73 Product specification P80CL580; P83CL580 0 MLA586 0 MGD682 V DD ...
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... scale (1) ( 0.42 0.22 21.65 11.1 15.8 0.75 0.30 0.14 21.35 11.0 15.2 0.017 0.0087 0.85 0.44 0.62 0.03 0.012 0.0055 0.84 0.43 0.60 REFERENCES JEDEC EIAJ 74 P80CL580; P83CL580 detail 1.6 1.45 2.25 0.2 0.1 1.4 1.30 0.063 0.057 0.089 0.008 0.004 0.055 0.051 EUROPEAN PROJECTION Product specification SOT190 ...
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... Mar scale (1) ( 0.50 0.25 20.1 14.1 24.2 1 0.35 0.14 19.9 13.9 23.6 REFERENCES JEDEC EIAJ 75 P80CL580; P83CL580 18.2 1.0 1.4 1.95 0.2 0.2 17.6 0.6 1.2 EUROPEAN PROJECTION Product specification ...
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... This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Mar 14 P80CL580; P83CL580 If wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 14 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 77 Product specification P80CL580; P83CL580 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 NOTES 78 Product specification ...
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... Philips Semiconductors Low voltage 8-bit microcontrollers with 2 UART, I C-bus and ADC 1997 Mar 14 P80CL580; P83CL580 NOTES 79 Product specification ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + ...