p80cl580 NXP Semiconductors, p80cl580 Datasheet - Page 20

• Manufacturer Part Number: p80cl580
• Description: Low Voltage 8-bit Microcontrollers With Uart, I2c-bus And Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11.4
In addition to Timer T2 and the standard timers, a
Watchdog Timer (consisting of an 11-bit prescaler and an
8-bit timer) is also incorporated.
The Watchdog Timer is controlled by the Watchdog
Enable pin (EWN). When EWN = 0, the timer is enabled
and the Power-down mode is disabled. When EWN = 1,
the timer is disabled and the Power-down mode is
enabled. In the Idle mode the Watchdog Timer and reset
circuitry remain active.
The Watchdog Timer is shown in Fig. 12.
The timer frequency is derived from the oscillator
frequency using the following formula:
1997 Mar 14
f
handbook, full pagewidth
timer
Low voltage 8-bit microcontrollers with
UART, I
=
Watchdog Timer
-------------------------------- -
EWN
12 2048
f osc /12
f
osc
2
C-bus and ADC
write
T3
Fig.12 Functional diagram of the T3 Watchdog Timer.
PRESCALER
11-BIT
CLEAR
TIMER T3 (8-BIT)
PCON.4
INTERNAL BUS
INTERNAL BUS
LOAD
20
CLEAR
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin. To
prevent a system reset the timer must be reloaded in time
by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer reloading and the
occurrence of a reset is dependent upon the reloaded
value. For example, this time period may range from 2 ms
to 500 ms when using an oscillator frequency
f
WLE
osc
LOADEN
= 12 MHz.
internal
reset
overflow
LOADEN
PD
P80CL580; P83CL580
PCON.1
Product specification
V DD
P
R RST
MGD678
RST