p87c51mc2 NXP Semiconductors, p87c51mc2 Datasheet - Page 22

• Manufacturer Part Number: p87c51mc2
• Description: 80c51 8-bit Microcontroller Family With Extended Memory
• Manufacturer: NXP Semiconductors

Notes:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause
4. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0Hz.
2001 Apr 06
Philips Semiconductors
Shift Register
SPI Interface
SYMBOL FIGURE(S)
t
t
t
t
t
t
SPILEAD
SPICLKH
SPICLKL
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
t
SPICYC
SPIDSU
t
t
t
t
t
t
t
SPILAG
SPIDIS
t
SPIDH
SPIOH
QVXH
XHQX
t
SPIDV
t
t
XHDX
XHDV
XLXL
f
SPIA
SPIR
SPIF
damage to Port 0 drivers.
SPI
8, 9, 10, 11
8, 9, 10, 11
8, 9, 10, 11
8, 9, 10, 11 Data setup time (Master or Slave)
8, 9, 10, 11 Data hold time (Master or Slave)
8, 9, 10, 11
8, 9, 10, 11 Output data hold time
8, 9, 10, 11
8, 9, 10, 11
10, 11
10, 11
10, 11
10, 11
7
7
7
7
7
Serial port clock cycle time
Output data setup to clock rising
edge
Output data hold after clock rising
edge
Input data hold after clock rising
edge
Clock rising edge to input data valid
Operating frequency
- 3.0MHz
- 6.0MHz
Cycle time
- 3.0MHz
- 6.0MHz
Enable lead time (Slave)
- 3.0MHz
- 6.0MHz
Enable lag time (Slave)
- 3.0MHz
- 6.0MHz
SPICLK high time
- Master
- Slave
SPICLK low time
- Master
- Slave
Access time (Slave)
Disable time (Slave)
- 3.0MHz
- 6.0MHz
Enable to output data valid
- 3.0MHz
- 6.0MHz
Rise time
- SPI outputs (SPICLK,MOSI, MISO)
- SPI inputs (SPICLK,MOSI, MISO,
SS)
Fall time
- SPI outputs (SPICLK,MOSI, MISO)
- SPI inputs (SPICLK,MOSI, MISO,
SS)
PARAMETER
5t
t
CLCL
CLCL
6t
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
333
CLCL
Variable Clock
0
0
0
-
-
-
-
-221
-50
2.7V < VDD < 5.5V
5t
CLCL
22
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3.0
-
-
4
-222
f
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
OSC
MIN
500
195
333
34
0
0
0
-
-
-
-
=12MHz
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
195
3.0
-
-
4
5t
t
CLCL
CLCL
6t
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
P87C51MB2/P87C51MC2
MIN
333
166
CLCL
Variable Clock
0
0
0
0
-110
-25
4.5V < VDD < 5.5V
5t
CLCL
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3.0
6.0
4
-111
Preliminary specification
f
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
OSC
250
333
166
98
17
0
0
0
0
=24MHz
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3.0
6.0
97
4
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns